Background:
As we can see from the reference above, the HSE subsystem has its own Dflash which is the so called"Secure NVM" and outside of HSE Subsystem is another Dflash called"Application NVM".
The HSE Secure NVM is used to stored some most critical important data like keys and counters, and this is becoming a mainstream requirement from most OEMs from cyber-security perspective.
Problem Description:
In some certain case that the whole system access the "Application NVM" and "Secure NVM" at the same time, maybe in a short time, it will cause a Bus Conflict, which result in a failure case of the Micro controller. The case could happen during the vehicle manufacture production line which will use some of the UDS client to write the calibration value together with the keys.
Actually this is due to that the "Application NVM" and "Secure NVM" are originally designed as a same dflash with its programmer. When you have a HSE Firmwire configured, this orginal dflash will be seperated into 2 part D-flash，one is for HSE to use, the secure NVM, one is the Application NVM for the non-HSE subsystem to use.
Questions:
1. What is the complete description of this failure case? For example, within what time frame would sharing a programmer lead to conflicts, such as 10ms? What are the specific manifestations, causes, and outcomes of the conflict? Is there any related testing to prove this?
2. Under the design of K344, are there any non-chip-related solutions?
A. Through software configuration: Are there any configurations in the chip that can resolve the issue through bus isolation or timing methods? For instance, when using D flash to store information for the main core (non-network security related), could I intentionally control the HSE storage task to be pending, waiting until it ends before proceeding with operations? Or, when using the main core's non-network security bus, could I disallow the use of network security bus resources, waiting until they are free before using them?
B. By adjusting the timing of the data injection from the host computer: Could I intentionally adjust the timing of the data that needs to be stored from the host computer (such as UDS command timing), first storing non-network security related information, then deliberately delaying for 1 second before storing security information (such as keys)?
3. Are there other chips that can solve this problem? Could you briefly introduce them?
