S32K344 - FlexCAN - Legacy RxFIFO

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S32K344 - FlexCAN - Legacy RxFIFO

519 Views
kyf
Contributor V

Hello NXP team!

What are the steps to configure FlexCAN into Legacy RxFIFO mode ?

 

I have done so far:

1. Configure PIN from pin tool

2. Configure FlexCAN3 + IntCtrl from peripheral tool

In the code....

3. Init clocks

4. Init interrupt controller and FlexCAN3 interrupt +set IRQ priority

5. Init FlexCAN3 peripheral (FlexCAN_Ip_Init)

6. Setup ID filter Table for RxFIFO (FlexCAN_Ip_ConfigRxFifo)

7. Put FlexCAN peripheral into Start Mode (FlexCAN_Ip_SetStartMode)

8. Enter a while(1) loop and wait for IRQ of FlexCAN.

 

9. I'm sending a packet via my PC by using a usb to can controller of PEAK-System.

 

10. I get a message that the bus is heavy and I don't see anything changing until I stop the communication myself.

 

I've studied the RM of S32K344 regarding FlexCAN and I have configured in the past the Enchanced RxFIFO for FlexCAN0 but it is not supported for FlexCAN1,2 and 3 so I need to setup the Legacy RxFIFO.

 

a. I've sent a message with the same ID as the ID used in the ID Filter table.

b. My bitrate is 500Kb in both devices (my MCU and PCAN controller).

c.FlexCAN clock is 16MHz

d. My configurations are those:

 

     .cfg =
     {
          //CAN periph configs
          .flexcanMode                    = FLEXCAN_NORMAL_MODE,
          .ctrlOptions                    = (FLEXCAN_IP_PROTOCOL_EXCEPTION_U32),
          .fd_enable                      = false,
          .enhCbtEnable                   = false,
          .bitRateSwitch                  = false,
          .bitrate                        = {2, 2, 3, 4, 2},
          .bitrate_cbt                    = {2, 2, 3, 4, 2},

          //CAN IRQ callback pointers
          .Callback                       = flexcan3_cb,
          .ErrorCallback                  = NULL_PTR,

          // MailBox configs
          .max_num_mb                     = 32,
          .payload                        = {FLEXCAN_PAYLOAD_SIZE_8, FLEXCAN_PAYLOAD_SIZE_8, FLEXCAN_PAYLOAD_SIZE_8},

          //RxFIFO configs
          .is_rx_fifo_needed              = true ,
          .num_id_filters                 = FLEXCAN_RX_FIFO_ID_FILTERS_8,
          .transfer_type                  = FLEXCAN_RXFIFO_USING_INTERRUPTS,

          //Enchanced RxFIFO configs
          .is_enhanced_rx_fifo_needed     = false,
          .num_enhanced_std_id_filters    = 0,
          .num_enhanced_ext_id_filters    = 0,
          .num_enhanced_watermark         = 0,
     },

 

 

 

 

Kind regards,

kyf

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2 Replies

483 Views
kyf
Contributor V

Thank you @PetrS for reaching out !!

I will try your suggestions and read the document that you have shared with me and I'll be back with comments this evening.

 

 

Kind regards,

kyf

 

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505 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

steps you have looks correct, and it is similar as for enhanced RXFIFO, just configure legacy RXFIFO.
You should also add configuration of mask registers between steps 6 and 7 and after step 7 call FlexCAN_Ip_RxFifo.

The Legacy RXFIFO use case is explained in https://www.nxp.com/webapp/Download?colCode=18_S32K3XX_COMMUNICATION_MODULES_FLEXCAN_WITH_RTD

If you see any issues with communication just read ESR1/ECR registers, if any errors are detected. 

BR, Petr

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