S32K344-Can DataFlash and CodeFlash be operated at the same time?

[Simon-Liu]

Hello

Is it possible to write or erase DataFlash and CodeFlash at the same time?

BestRegards,

Simon

[Senlent]

Hi@Simon-Liu

It depends on the situation. For example, AN13388 describes it this way.

The Flash memory can perform multiple reads between different blocks by a single, dual or quad read feature, where in a multi-core scenario, if there are multiple threads running in parallel (on different sections/blocks of memory) those threads can occur simultaneously by a dual or quad read, this feature is controlled internally and not by the user. It also has the “Read-While-Write” (RWW) feature to be able to perform a read and a write simultaneously (applies only when operations are in different blocks); for example, in the S32K324, if the Core 0 application is performing a write process in block 0, then the Core 1 at the same time can read a data stored in the data flash block.

[Simon-Liu]

Hi @Senlent 

Thanks for your answer.

I know that simultaneous reading is possible and there is a "read while writing" function. What I want to confirm is whether simultaneous programming or simultaneous erasing is supported.

BestRegards,

Simon

[Senlent]

Hi@Simon-Liu

Simultaneous read and write operations on the same block are not supported. It is possible to perform read and write operations on different blocks separately.

[Simon-Liu]

Hi @Senlent 

Is it possible to erase one block while erasing another block?

[Senlent]

Hi@Simon-Liu

For single-core and interlocked cores, there is no such problem, because only one CPU core can work.

For multi-core, it is possible, which has been explained in the first answer.

[Simon-Liu]

Hi @Senlent 

I understand the first answer, "if the Core 0 application is performing a write process in block 0, then the Core 1 at the same time can read a data stored in the data flash block." Because if one block is read while another block is written, only one core will set the PGM and EHV bits of the C40 register MCR.
So if two cores write to two blocks at the same time, how can the other core set the PGM and EHV bits again if one core has already set the PGM and EHV bits?

[Senlent · Accepted solution]

Hi@Simoin-Liu

This is a summary of some consultations between me and our AE colleagues.

At the hardware level, it supports multi-core parallel access to different blocks.

As for whether there is a conflict if multiple cores access the same register at the same time,

this actually needs to be avoided by the fls driver.

However, the fls driver we currently provide cannot provide multi-core parallel access to

different blocks.

[Simon-Liu]

Hi @Senlent 

Thank you for your response.

[Senlent]

Hi@Simon-Liu

Please be patient. I need to confirm whether multiple cores can write to different blocks simultaneously.