S32K328: Ethernet packets are not transmitted with MAC-MAC connection

[sathishkumar_sunmugavel]

Hi Everyone,

I am working on an S32K328 MCU and trying to establish Ethernet communication using a MAC-to-MAC connection. In my setup, the S32K328 GMAC is connected via RGMII interface to a switch MAC, and the switch is further connected to a PHY.

I am able to see that the link status is up, but no Tx or Rx traffic is observed. I suspect this could be related to clock configuration, but I am not sure what needs to be verified.

Could you please clarify the basic requirements for a MAC-to-MAC connection and provide details on:

1. Clock configuration and source requirements for RGMII in MAC-to-MAC mode.

2. Any specific GMAC register configurations or settings needed for this setup.

3. Whether any RGMII delay or skew adjustments are required on the S32K328 side.

Thank you for your support.

Best regards,
Sathish.

[sathishkumar_sunmugavel]

Please find the existing clock configuration here

[sathishkumar_sunmugavel]

Hello All,

I have a few additional questions regarding the S32K328 clock setup and GMAC configuration:

1. I couldn’t find the clock diagram for the S32K328 in the Reference Manual (Rev. 6.1). Can I refer to the S32K358 clock diagram instead, since both devices belong to the same family?

2. In the S32K358 clock diagram, there are two external clocks — EMAC_MII_RX_CLK and EMAC_MII_RMII_TX_CLK. It appears that only EMAC_MII_RMII_TX_CLK is connected to EMAC_CLK_RX and EMAC_CLK_TX. If this external clock is not available, what is the recommended alternative clock source?

   • I cannot use FXOSC → PLL → GMAC, since I need a 125 MHz clock for the RGMII interface, and deriving this frequency from the PLL would affect other clock domains.

3. Is there any specific configuration required for the DCMRWF3 register in this setup?

4. Does the S32K328 device include a PLLAUX (auxiliary PLL) similar to the S32K358, and can it be used as a clock source for the GMAC?
   
   
   

Best Regards,
Sathish.

[sathishkumar_sunmugavel]

5. For the RGMII interface, could you please confirm the direction of the TXCLK and RXCLK pins?

Which signal is expected to be input and which one output on the S32K328 side?

[PavelL · Accepted solution]

Hello @sathishkumar_sunmugavel ,

Please check my post on S32K358 - GMAC Clock Configuration - NXP Community . I believe I answered most of the questions there.

Here's the rest:

• You have no choice - PLL needs to be used - due to clock precision and stability
• There is PLLAUX in S32K328

Just repeat that the latest available RM is Rev. 11 .

Best regards,

Pavel

[sathishkumar_sunmugavel]

Hi @PavelL 

Thank you so much for the valuable inputs. The issue is resolved after adding the below line. 

IP_DCM_GPR->DCMRWF1|=DCM_GPR_DCMRWF1_MAC_CONF_SEL(0x01) |DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN_MASK;

But could you please confirm why this tx clock loop back is required?

Best Regards,
Sathish.