S32K322 Initialized data segments are not initialized incorrect value or get corrupted

AbdNxp · ‎04-07-2025

Hi Dear NXP and contributors,

I am stuck in very critical issue regarding corruption of initialized data segment.

I am using NXP S32K322 MCU, there are two code section c0 and c1 , c0 starts with 0x000000 address (I use it for bootloader) while 0x500200 for application code flash.

Before I begin, listing sdk details from RTD header file:-

* Autosar Version : 4.7.0
* Autosar Revision : ASR_REL_4_7_REV_0000
* Autosar Conf.Variant :
* SW Version : 3.0.0
* Build Version : S32K3_RTD_3_0_0_P01_HF02_D2305_ASR_REL_4_7_REV_0000_20230331

* IDE : S32DS

* MCU : S32K322 Cortex _M7_0

My application some time encounter with hardfault, which I debugged and found that just after control jumped to application from the bootloader few static variable (be pointer or normal variable) either not initialized with the constant value that is assigned during initialization and few pointer variables in RTD its self are not initialized with correct address.

for example ,

1. I am using freeRTOS where variable xFreeBytesRemaining in heap_2 should be initialize with configADJUSTED_HEAP_SIZE but some time its initial value is 0. which is invalid value and because of this task/software timer/mutex e.tc create fails.

2. Similarly variable Power_Ip_pxMC_RGM, which suppose to have default value defined by macro IP_MC_RGM_BASE. But some time this variable get initialize with some invalid value, which definitely causes illegal memory access causing hard fault.

I am attaching my bootloader and application linker files, application configuration file.

Below function where Bootloader jumps to application

void bootApp(void)

{

if (periPheralInitStatus.spiInitStatus)

{

SPIDeInit();

C40_Ip_Abort();

Clock_Ip_DisableModuleClock(LPSPI2_CLK);

}

if (periPheralInitStatus.canInitStatus)

{

IntCtrl_Ip_DisableIrq (FlexCAN3_1_IRQn);

CAN3DeInit();

Clock_Ip_DisableModuleClock(FLEXCAN3_CLK);

}

if(periPheralInitStatus.timer0InitStatus)

{

IntCtrl_Ip_DisableIrq(PIT0_IRQn);

TIMERDeInit();

Clock_Ip_DisableModuleClock(PIT0_CLK);

}

WDTReset();

Bootup_Application(0x00500800);

}

void Bootup_Application(const uint32_t app_StarAddress)

{

static void (*jump_to_application)(void);

appStack = *((uint32_t *)(app_StarAddress));

appEntry = *((uint32_t *)(app_StarAddress + 4));

jump_to_application = (void (*)(void))appEntry;

S32_SCB->VTOR = (uint32_t)app_StarAddress;

/* ASM_KEYWORD("cpsid i"); */

__asm volatile ("cpsid i" : : : "memory");

__asm volatile ("msr msp, %0" : : "r" (appStack) : "sp");

__asm volatile ("MSR psp, %0\n" : : "r" (appStack) : "memory");

jump_to_application();

}

Below is application main function

void AppMain(void)

{

GPIOInit();

WDTInit();

WDTReset();

Power_Ip_Init(&Power_Ip_HwIPsConfigPB);

BoardInit();

WDTReset();

/*This is what I was talking, here I cross verify the freeHeap before creating tasks*/

if ((configTOTAL_HEAP_SIZE - != xPortGetFreeHeapSize())

{

xPortAppInitFreeHeapSize();

}

OSInit(); //Creats the task

OsStart(); // just start the scheduler

while(1); //if stuct here , external watch dog will reset the softeare.

}

Need Help urgently.

Thanks & Regards

danielmartynek · ‎04-08-2025

Hi @AbdNxp,

The S32K322 MCU has two application cores, I understand the the secondary core is disabled.

Ca you share more information about the exception? Is it a MemManage fault or a BusFault?

Can you check the addresses of the variables just before the jump and use watchpoints on them?

What do you mean by "just after the jump", where do you halt it?

Are some of the variable initialized in the bootloader already? You did not share the startup code of the two projects.

Thanks,

Daniel

AbdNxp · ‎04-08-2025

Hi

I am using two power modes

mode0 is RUN mode, and mode1 is STANDBY mode.

I have attached few snapshot from configuration tool, that may help my configuation.

"What I mean by after jumping from bootloader to application?"

Every reset bootloader run (starting at 0x00400000 which is c0 of flash memory) it initializes CAN SPI, timer,does read /write to internal flash memory.

Once bootloader met certain conditions to jump to application it jumps to address 0x00500800 (application start address is 0x00500200), sell below application linler file content.

HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00004000;

__STANDBY_RAM_LIMIT_END = 0x20407FFF; /* 32Kbyte for standby ram */

ENTRY(Reset_Handler)

MEMORY

{

int_pflash : ORIGIN = 0x00500000 + 0x200, LENGTH = 0x001D4000 - 0x200 /* 2048KB - 176KB (sBAF + HSE)*/

/*int_pflash : ORIGIN = 0x00400000, LENGTH = 0x001D4000 /*2048KB - 176KB (sBAF + HSE)*/

int_dflash : ORIGIN = 0x10000000, LENGTH = 0x00020000 /* 128KB */

int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */

int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x0000F000 /* 60KB */

int_stack_dtcm : ORIGIN = 0x2000F000, LENGTH = 0x00001000 /* 4KB */

int_sram : ORIGIN = 0x20400000, LENGTH = 0x0000CA00 /* (50KB-VRN)32KB, needs to include int_sram_fls_rsv */

int_sram_fls_rsv : ORIGIN = 0x2040CA00, LENGTH = 0x00000100

int_sram_no_cacheable : ORIGIN = 0x2040CB00, LENGTH = 0x00003000 /* (12KB-VRN)16KB , needs to include int_sram_results */

int_sram_results : ORIGIN = 0x2040FB00, LENGTH = 0x00000100

int_sram_shareable : ORIGIN = 0x2040FC00, LENGTH = 0x00000400 /* (1KB - VRN)16KB */

ram_rsvd2 : ORIGIN = 0x20410000, LENGTH = 0 /* End of SRAM */

/*********************************************************************************/

int_dtcm_1_bd : ORIGIN = 0x21400000, LENGTH = 0x00010000 /* 64K (VRN)*/

/*********************************************************************************/

}

SECTIONS

{

.pflash :

{

KEEP(*(.boot_header))

. = ALIGN(2048);

__text_start = .;

__interrupts_init_start = .;

KEEP(*(.intc_vector))

. = ALIGN(4);

__interrupts_init_end = .;

KEEP(*(.core_loop))

. = ALIGN(4);

*(.startup)

. = ALIGN(4);

*(.systeminit)

. = ALIGN(4);

*(.text.startup)

. = ALIGN(4);

*(.text)

*(.text*)

. = ALIGN(4);

*(.mcal_text)

. = ALIGN(4);

*(.acmcu_code_rom)

. = ALIGN(4);

__acfls_code_rom_start = .;

*(.acfls_code_rom)

. = ALIGN(4);

__acfls_code_rom_end = .;

KEEP(*(.init))

. = ALIGN(4);

KEEP(*(.fini))

. = ALIGN(4);

*(.rodata)

*(.rodata*)

. = ALIGN(4);

*(.mcal_const_cfg)

. = ALIGN(4);

*(.mcal_const)

. = ALIGN(4);

__init_table = .;

KEEP(*(.init_table))

. = ALIGN(4);

__zero_table = .;

KEEP(*(.zero_table))

} > int_pflash

. = ALIGN(4);

__text_end = .;

__sram_data_rom = __text_end;

.sram_bss (NOLOAD) :

{

. = ALIGN(8);

__standby_ram_begin__ = .;

*(.standby_data)

. = ALIGN(8);

__standby_ram_end__ = .;

. = ALIGN(16);

__sram_bss_start = .;

*(.bss)

*(.bss*)

. = ALIGN(16);

*(.mcal_bss)

. = ALIGN(4);

__sram_bss_end = .;

} > int_sram

.sram_data : AT(__sram_data_rom)

{

. = ALIGN(4);

__sram_data_begin__ = .;

. = ALIGN(4);

*(.ramcode)

. = ALIGN(4);

*(.data)

*(.data*)

. = ALIGN(4);

*(.mcal_data)

. = ALIGN(4);

__sram_data_end__ = .;

} > int_sram

__sram_data_rom_end = __sram_data_rom + (__sram_data_end__ - __sram_data_begin__);

/* heap section */

.heap (NOLOAD):

{

. += ALIGN(4);

_end = .;

end = .;

_heap_start = .;

. += HEAP_SIZE;

_heap_end = .;

} > int_sram

.acfls_code_ram :

{

acfls_code_ram_start = .;

*(.acfls_code_ram)

acfls_code_ram_stop = .;

} > int_sram_fls_rsv

__non_cacheable_data_rom = __sram_data_rom_end;

.non_cacheable_data : AT(__non_cacheable_data_rom)

{

. = ALIGN(4);

__non_cacheable_data_start__ = .;

*(.mcal_data_no_cacheable)

. = ALIGN(4);

*(.mcal_const_no_cacheable)

. = ALIGN(4);

HSE_LOOP_ADDR = .;

LONG(0x0);

__non_cacheable_data_end__ = .;

} > int_sram_no_cacheable

__non_cacheable_data_rom_end = __non_cacheable_data_rom + (__non_cacheable_data_end__ - __non_cacheable_data_start__);

.non_cacheable_bss (NOLOAD) :

{

. = ALIGN(16);

__non_cacheable_bss_start = .;

*(.mcal_bss_no_cacheable)

. = ALIGN(4);

__non_cacheable_bss_end = .;

} > int_sram_no_cacheable

.int_results (NOLOAD):

{

. = ALIGN(4);

KEEP(*(.int_results))

. += 0x100;

} > int_sram_results

__shareable_data_rom = __non_cacheable_data_rom_end;

.shareable_data : AT(__shareable_data_rom)

{

. = ALIGN(4);

__shareable_data_start__ = .;

KEEP(*(.mcal_shared_data))

. = ALIGN(4);

__shareable_data_end__ = .;

} > int_sram_shareable

__shareable_data_rom_end = __shareable_data_rom + (__shareable_data_end__ - __shareable_data_start__);

.int_vector :

{

. = ALIGN(2048);

__interrupts_ram_start = .;

. += __interrupts_init_end - __interrupts_init_start;

. = ALIGN(4);

__interrupts_ram_end = .;

} > int_dtcm

.shareable_bss (NOLOAD) :

{

. = ALIGN(16);

__shareable_bss_start = .;

*(.mcal_shared_bss)

. = ALIGN(4);

__shareable_bss_end = .;

} > int_sram_shareable

/********************************************************** VRN*/

__itcm0_code_rom = __shareable_data_rom_end;

.itcm0_code : AT(__itcm0_code_rom)

{

. = ALIGN(4);

__itcm0_code_start__ = .;

KEEP(*(.itcm0_code))

. = ALIGN(4);

__itcm0_code_end__ = .;

} > int_itcm

__itcm0_code_rom_end = __itcm0_code_rom + (__itcm0_code_end__ - __itcm0_code_start__);

__dtcm0_data_rom = __itcm0_code_rom_end;

.dtcm0_data : AT(__dtcm0_data_rom)

{

. = ALIGN(4);

__dtcm0_data_start__ = .;

KEEP(*(.dtcm0_data))

. = ALIGN(4);

__dtcm0_data_end__ = .;

} > int_dtcm

__dtcm0_data_rom_end = __dtcm0_data_rom + (__dtcm0_data_end__ - __dtcm0_data_start__);

__dtcm1_bd_data_rom = __dtcm0_data_rom_end;

.dtcm1_bd_data : AT(__dtcm1_bd_data_rom)

{

. = ALIGN(4);

__dtcm1_bd_data_start__ = .;

KEEP(*(.dtcm1_bd_data))

. = ALIGN(4);

__dtcm1_bd_data_end__ = .;

} > int_dtcm_1_bd

__dtcm1_bd_data_rom_end = __dtcm1_bd_data_rom + (__dtcm1_bd_data_end__ - __dtcm1_bd_data_start__);

/**********************************************************/

__Stack_dtcm_end = ORIGIN(int_stack_dtcm);

__Stack_dtcm_start = ORIGIN(int_stack_dtcm) + LENGTH(int_stack_dtcm);

__INT_SRAM_START = ORIGIN(int_sram);

__INT_SRAM_END = ORIGIN(ram_rsvd2);

__INT_ITCM_START = ORIGIN(int_itcm);

__INT_ITCM_END = ORIGIN(int_itcm) + LENGTH(int_itcm);

__INT_DTCM_START = ORIGIN(int_dtcm);

__INT_DTCM_END = ORIGIN(int_dtcm) + LENGTH(int_dtcm) + LENGTH(int_stack_dtcm);

/*********************************************************VRN*/

__INT_DTCM_1_BD_START = ORIGIN(int_dtcm_1_bd);

__INT_DTCM_1_BD_END = ORIGIN(int_dtcm_1_bd) + LENGTH(int_dtcm_1_bd);

__RAM_DTCM1_BD_DATA_START = __dtcm1_bd_data_start__;

__ROM_DTCM1_BD_DATA_START = __dtcm1_bd_data_rom;

__ROM_DTCM1_BD_DATA_END = __dtcm1_bd_data_rom_end;

__DTCM1_BD_START = ORIGIN(int_dtcm_1_bd);

__DTCM1_BD_SIZE = 0x10; /*64 kbyte*/

/**********************************************************/

__RAM_SHAREABLE_START = ORIGIN(int_sram_shareable);

__RAM_SHAREABLE_END = ORIGIN(int_sram_shareable) + LENGTH(int_sram_shareable);

__RAM_SHAREABLE_SIZE = 0xE; /* 16kbyte in power of 2 */

__ROM_SHAREABLE_START = __shareable_data_rom;

__ROM_SHAREABLE_END = __shareable_data_rom_end;

__RAM_NO_CACHEABLE_START = ORIGIN(int_sram_no_cacheable);

__RAM_NO_CACHEABLE_END = ORIGIN(int_sram_shareable)-1;

__RAM_NO_CACHEABLE_SIZE = 0xE; /* 16kbyte in power of 2 */

__ROM_NO_CACHEABLE_START = __non_cacheable_data_rom;

__ROM_NO_CACHEABLE_END = __non_cacheable_data_rom_end;

__RAM_CACHEABLE_START = __sram_data_begin__;

__RAM_CACHEABLE_END = ORIGIN(int_sram_no_cacheable)-1;

__RAM_CACHEABLE_SIZE = 0xE; /* 16kbyte in power of 2 */

__ROM_CACHEABLE_START = __sram_data_rom;

__ROM_CACHEABLE_END = __sram_data_rom_end;

__ROM_CODE_START = ORIGIN(int_pflash);

__ROM_DATA_START = ORIGIN(int_dflash);

__BSS_SRAM_START = __sram_bss_start;

__BSS_SRAM_END = __sram_bss_end;

__BSS_SRAM_SIZE = __sram_bss_end - __sram_bss_start;

__BSS_SRAM_NC_START = __non_cacheable_bss_start;

__BSS_SRAM_NC_SIZE = __non_cacheable_bss_end - __non_cacheable_bss_start;

__BSS_SRAM_NC_END = __non_cacheable_bss_end;

__BSS_SRAM_SH_START = __shareable_bss_start;

__BSS_SRAM_SH_SIZE = __shareable_bss_end - __shareable_bss_start;

__BSS_SRAM_SH_END = __shareable_bss_end;

__RAM_INTERRUPT_START = __interrupts_ram_start;

__INIT_INTERRUPT_START = __interrupts_init_start;

__INIT_INTERRUPT_END = __interrupts_init_end;

__RAM_ITCM0_CODE_START = __itcm0_code_start__;

__ROM_ITCM0_CODE_START = __itcm0_code_rom;

__ROM_ITCM0_CODE_END = __itcm0_code_rom_end;

__RAM_DTCM0_DATA_START = __dtcm0_data_start__;

__ROM_DTCM0_DATA_START = __dtcm0_data_rom;

__ROM_DTCM0_DATA_END = __dtcm0_data_rom_end;

__INIT_TABLE = __init_table;

__ZERO_TABLE = __zero_table;

__RAM_INIT = 1;

__ITCM_INIT = 1;

__DTCM_INIT = 1;

/**********************************************************/

__DTCM1_BD_INIT = 1;

/**********************************************************/

Fls_ACEraseRomStart = __acfls_code_rom_start;

Fls_ACEraseRomEnd = __acfls_code_rom_end;

Fls_ACEraseSize = (__acfls_code_rom_end - __acfls_code_rom_start) / 4; /* Copy 4 bytes at a time*/

Fls_ACWriteRomStart = __acfls_code_rom_start;

Fls_ACWriteRomEnd = __acfls_code_rom_end;

Fls_ACWriteSize = (__acfls_code_rom_end - __acfls_code_rom_start) / 4; /* Copy 4 bytes at a time*/

_ERASE_FUNC_ADDRESS_ = ADDR(.acfls_code_ram);

_WRITE_FUNC_ADDRESS_ = ADDR(.acfls_code_ram);

__ENTRY_VTABLE = __INIT_INTERRUPT_START;

__CORE0_VTOR = __INIT_INTERRUPT_START;

__CORE1_VTOR = __INIT_INTERRUPT_START;

__CORE2_VTOR = __INIT_INTERRUPT_START;

__INDEX_COPY_CORE2 = 3; /* This symbol is used to initialize data of ITCM/DTCM for CORE2 */

ASSERT(__standby_ram_end__ <= __STANDBY_RAM_LIMIT_END, "Memory for standby ram overflow")

}

see bootloader Linker below:-

HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00004000;

__STANDBY_RAM_LIMIT_END = 0x20407FFF; /* 32Kbyte for standby ram */

ENTRY(Reset_Handler)

MEMORY

{

/*int_pflash : ORIGIN = 0x00500000 + 0x200, LENGTH = 0x001D4000 - 0x200 /* 2048KB - 176KB (sBAF + HSE)*/

int_pflash : ORIGIN = 0x00400000, LENGTH = 0x001D4000 /*2048KB - 176KB (sBAF + HSE)*/

int_dflash : ORIGIN = 0x10000000, LENGTH = 0x00020000 /* 128KB */

int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */

int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x0000F000 /* 60KB */

int_stack_dtcm : ORIGIN = 0x2000F000, LENGTH = 0x00001000 /* 4KB */

int_sram : ORIGIN = 0x20400000, LENGTH = 0x0000CA00 /* (50KB-VRN)32KB, needs to include int_sram_fls_rsv */

int_sram_fls_rsv : ORIGIN = 0x2040CA00, LENGTH = 0x00000100

int_sram_no_cacheable : ORIGIN = 0x2040CB00, LENGTH = 0x00003000 /* (12KB-VRN)16KB , needs to include int_sram_results */

int_sram_results : ORIGIN = 0x2040FB00, LENGTH = 0x00000100

int_sram_shareable : ORIGIN = 0x2040FC00, LENGTH = 0x00000400 /* (1KB - VRN)16KB */

ram_rsvd2 : ORIGIN = 0x20410000, LENGTH = 0 /* End of SRAM */

/*********************************************************************************/

int_dtcm_1_bd : ORIGIN = 0x21400000, LENGTH = 0x00010000 /* 64K (VRN)*/

/*********************************************************************************/

}

SECTIONS

{

.pflash :

{

KEEP(*(.boot_header))

. = ALIGN(2048);

__text_start = .;

__interrupts_init_start = .;

KEEP(*(.intc_vector))

. = ALIGN(4);

__interrupts_init_end = .;

KEEP(*(.core_loop))

. = ALIGN(4);

*(.startup)

. = ALIGN(4);

*(.systeminit)

. = ALIGN(4);

*(.text.startup)

. = ALIGN(4);

*(.text)

*(.text*)

. = ALIGN(4);

*(.mcal_text)

. = ALIGN(4);

*(.acmcu_code_rom)

. = ALIGN(4);

__acfls_code_rom_start = .;

*(.acfls_code_rom)

. = ALIGN(4);

__acfls_code_rom_end = .;

KEEP(*(.init))

. = ALIGN(4);

KEEP(*(.fini))

. = ALIGN(4);

*(.rodata)

*(.rodata*)

. = ALIGN(4);

*(.mcal_const_cfg)

. = ALIGN(4);

*(.mcal_const)

. = ALIGN(4);

__init_table = .;

KEEP(*(.init_table))

. = ALIGN(4);

__zero_table = .;

KEEP(*(.zero_table))

} > int_pflash

. = ALIGN(4);

__text_end = .;

__sram_data_rom = __text_end;

.sram_bss (NOLOAD) :

{

. = ALIGN(8);

__standby_ram_begin__ = .;

*(.standby_data)

. = ALIGN(8);

__standby_ram_end__ = .;

. = ALIGN(16);

__sram_bss_start = .;

*(.bss)

*(.bss*)

. = ALIGN(16);

*(.mcal_bss)

. = ALIGN(4);

__sram_bss_end = .;

} > int_sram

.sram_data : AT(__sram_data_rom)

{

. = ALIGN(4);

__sram_data_begin__ = .;

. = ALIGN(4);

*(.ramcode)

. = ALIGN(4);

*(.data)

*(.data*)

. = ALIGN(4);

*(.mcal_data)

. = ALIGN(4);

__sram_data_end__ = .;

} > int_sram

__sram_data_rom_end = __sram_data_rom + (__sram_data_end__ - __sram_data_begin__);

/* heap section */

.heap (NOLOAD):

{

. += ALIGN(4);

_end = .;

end = .;

_heap_start = .;

. += HEAP_SIZE;

_heap_end = .;

} > int_sram

.acfls_code_ram :

{

acfls_code_ram_start = .;

*(.acfls_code_ram)

acfls_code_ram_stop = .;

} > int_sram_fls_rsv

__non_cacheable_data_rom = __sram_data_rom_end;

.non_cacheable_data : AT(__non_cacheable_data_rom)

{

. = ALIGN(4);

__non_cacheable_data_start__ = .;

*(.mcal_data_no_cacheable)

. = ALIGN(4);

*(.mcal_const_no_cacheable)

. = ALIGN(4);

HSE_LOOP_ADDR = .;

LONG(0x0);

__non_cacheable_data_end__ = .;

} > int_sram_no_cacheable

__non_cacheable_data_rom_end = __non_cacheable_data_rom + (__non_cacheable_data_end__ - __non_cacheable_data_start__);

.non_cacheable_bss (NOLOAD) :

{

. = ALIGN(16);

__non_cacheable_bss_start = .;

*(.mcal_bss_no_cacheable)

. = ALIGN(4);

__non_cacheable_bss_end = .;

} > int_sram_no_cacheable

.int_results (NOLOAD):

{

. = ALIGN(4);

KEEP(*(.int_results))

. += 0x100;

} > int_sram_results

__shareable_data_rom = __non_cacheable_data_rom_end;

.shareable_data : AT(__shareable_data_rom)

{

. = ALIGN(4);

__shareable_data_start__ = .;

KEEP(*(.mcal_shared_data))

. = ALIGN(4);

__shareable_data_end__ = .;

} > int_sram_shareable

__shareable_data_rom_end = __shareable_data_rom + (__shareable_data_end__ - __shareable_data_start__);

.int_vector :

{

. = ALIGN(2048);

__interrupts_ram_start = .;

. += __interrupts_init_end - __interrupts_init_start;

. = ALIGN(4);

__interrupts_ram_end = .;

} > int_dtcm

.shareable_bss (NOLOAD) :

{

. = ALIGN(16);

__shareable_bss_start = .;

*(.mcal_shared_bss)

. = ALIGN(4);

__shareable_bss_end = .;

} > int_sram_shareable

/********************************************************** VRN*/

__itcm0_code_rom = __shareable_data_rom_end;

.itcm0_code : AT(__itcm0_code_rom)

{

. = ALIGN(4);

__itcm0_code_start__ = .;

KEEP(*(.itcm0_code))

. = ALIGN(4);

__itcm0_code_end__ = .;

} > int_itcm

__itcm0_code_rom_end = __itcm0_code_rom + (__itcm0_code_end__ - __itcm0_code_start__);

__dtcm0_data_rom = __itcm0_code_rom_end;

.dtcm0_data : AT(__dtcm0_data_rom)

{

. = ALIGN(4);

__dtcm0_data_start__ = .;

KEEP(*(.dtcm0_data))

. = ALIGN(4);

__dtcm0_data_end__ = .;

} > int_dtcm

__dtcm0_data_rom_end = __dtcm0_data_rom + (__dtcm0_data_end__ - __dtcm0_data_start__);

__dtcm1_bd_data_rom = __dtcm0_data_rom_end;

.dtcm1_bd_data : AT(__dtcm1_bd_data_rom)

{

. = ALIGN(4);

__dtcm1_bd_data_start__ = .;

KEEP(*(.dtcm1_bd_data))

. = ALIGN(4);

__dtcm1_bd_data_end__ = .;

} > int_dtcm_1_bd

__dtcm1_bd_data_rom_end = __dtcm1_bd_data_rom + (__dtcm1_bd_data_end__ - __dtcm1_bd_data_start__);

/**********************************************************/

__Stack_dtcm_end = ORIGIN(int_stack_dtcm);

__Stack_dtcm_start = ORIGIN(int_stack_dtcm) + LENGTH(int_stack_dtcm);

__INT_SRAM_START = ORIGIN(int_sram);

__INT_SRAM_END = ORIGIN(ram_rsvd2);

__INT_ITCM_START = ORIGIN(int_itcm);

__INT_ITCM_END = ORIGIN(int_itcm) + LENGTH(int_itcm);

__INT_DTCM_START = ORIGIN(int_dtcm);

__INT_DTCM_END = ORIGIN(int_dtcm) + LENGTH(int_dtcm) + LENGTH(int_stack_dtcm);

/*********************************************************VRN*/

__INT_DTCM_1_BD_START = ORIGIN(int_dtcm_1_bd);

__INT_DTCM_1_BD_END = ORIGIN(int_dtcm_1_bd) + LENGTH(int_dtcm_1_bd);

__RAM_DTCM1_BD_DATA_START = __dtcm1_bd_data_start__;

__ROM_DTCM1_BD_DATA_START = __dtcm1_bd_data_rom;

__ROM_DTCM1_BD_DATA_END = __dtcm1_bd_data_rom_end;

__DTCM1_BD_START = ORIGIN(int_dtcm_1_bd);

__DTCM1_BD_SIZE = 0x10; /*64 kbyte*/

/**********************************************************/

__RAM_SHAREABLE_START = ORIGIN(int_sram_shareable);

__RAM_SHAREABLE_END = ORIGIN(int_sram_shareable) + LENGTH(int_sram_shareable);

__RAM_SHAREABLE_SIZE = 0xE; /* 16kbyte in power of 2 */

__ROM_SHAREABLE_START = __shareable_data_rom;

__ROM_SHAREABLE_END = __shareable_data_rom_end;

__RAM_NO_CACHEABLE_START = ORIGIN(int_sram_no_cacheable);

__RAM_NO_CACHEABLE_END = ORIGIN(int_sram_shareable)-1;

__RAM_NO_CACHEABLE_SIZE = 0xE; /* 16kbyte in power of 2 */

__ROM_NO_CACHEABLE_START = __non_cacheable_data_rom;

__ROM_NO_CACHEABLE_END = __non_cacheable_data_rom_end;

__RAM_CACHEABLE_START = __sram_data_begin__;

__RAM_CACHEABLE_END = ORIGIN(int_sram_no_cacheable)-1;

__RAM_CACHEABLE_SIZE = 0xF; /* 32kbyte in power of 2 */

__ROM_CACHEABLE_START = __sram_data_rom;

__ROM_CACHEABLE_END = __sram_data_rom_end;

__ROM_CODE_START = ORIGIN(int_pflash);

__ROM_DATA_START = ORIGIN(int_dflash);

__BSS_SRAM_START = __sram_bss_start;

__BSS_SRAM_END = __sram_bss_end;

__BSS_SRAM_SIZE = __sram_bss_end - __sram_bss_start;

__BSS_SRAM_NC_START = __non_cacheable_bss_start;

__BSS_SRAM_NC_SIZE = __non_cacheable_bss_end - __non_cacheable_bss_start;

__BSS_SRAM_NC_END = __non_cacheable_bss_end;

__BSS_SRAM_SH_START = __shareable_bss_start;

__BSS_SRAM_SH_SIZE = __shareable_bss_end - __shareable_bss_start;

__BSS_SRAM_SH_END = __shareable_bss_end;

__RAM_INTERRUPT_START = __interrupts_ram_start;

__INIT_INTERRUPT_START = __interrupts_init_start;

__INIT_INTERRUPT_END = __interrupts_init_end;

__RAM_ITCM0_CODE_START = __itcm0_code_start__;

__ROM_ITCM0_CODE_START = __itcm0_code_rom;

__ROM_ITCM0_CODE_END = __itcm0_code_rom_end;

__RAM_DTCM0_DATA_START = __dtcm0_data_start__;

__ROM_DTCM0_DATA_START = __dtcm0_data_rom;

__ROM_DTCM0_DATA_END = __dtcm0_data_rom_end;

__INIT_TABLE = __init_table;

__ZERO_TABLE = __zero_table;

__RAM_INIT = 1;

__ITCM_INIT = 1;

__DTCM_INIT = 1;

/**********************************************************/

__DTCM1_BD_INIT = 1;

/**********************************************************/

Fls_ACEraseRomStart = __acfls_code_rom_start;

Fls_ACEraseRomEnd = __acfls_code_rom_end;

Fls_ACEraseSize = (__acfls_code_rom_end - __acfls_code_rom_start) / 4; /* Copy 4 bytes at a time*/

Fls_ACWriteRomStart = __acfls_code_rom_start;

Fls_ACWriteRomEnd = __acfls_code_rom_end;

Fls_ACWriteSize = (__acfls_code_rom_end - __acfls_code_rom_start) / 4; /* Copy 4 bytes at a time*/

_ERASE_FUNC_ADDRESS_ = ADDR(.acfls_code_ram);

_WRITE_FUNC_ADDRESS_ = ADDR(.acfls_code_ram);

__ENTRY_VTABLE = __INIT_INTERRUPT_START;

__CORE0_VTOR = __INIT_INTERRUPT_START;

__CORE1_VTOR = __INIT_INTERRUPT_START;

__CORE2_VTOR = __INIT_INTERRUPT_START;

__INDEX_COPY_CORE2 = 3; /* This symbol is used to initialize data of ITCM/DTCM for CORE2 */

ASSERT(__standby_ram_end__ <= __STANDBY_RAM_LIMIT_END, "Memory for standby ram overflow")

}

If I am not wrong below function in startup.c is responsible for initializing the initialized and un initialized static and global variables both in bootloader and application.

void init_data_bss(void)
{
const Sys_CopyLayoutType * copy_layout;
const Sys_ZeroLayoutType * zero_layout;
const uint32 * rom;
const uint8 * rom8;
uint32 * ram;
uint8 * ram8;
uint8 dataPad;
uint32 len = 0U;
uint32 size = 0U;
uint32 i = 0U;
uint32 j = 0U;

const uint32 * initTable_Ptr = (uint32 *)__INIT_TABLE;
const uint32 * zeroTable_Ptr = (uint32*)__ZERO_TABLE;

/* Copy initialized table */
len = *initTable_Ptr;
initTable_Ptr++;
copy_layout = (const Sys_CopyLayoutType *)initTable_Ptr;
for(i = 0; i < len; i++)
{
rom = copy_layout[i].rom_start;
ram = copy_layout[i].ram_start;
size = (uint32)copy_layout[i].rom_end - (uint32)copy_layout[i].rom_start;
/* Make sure the data area to be copied must be aligned with 4. Then, copy 4 bytes at per one read */
dataPad = size & 0x3U;
for(j = 0UL; j < ((size - dataPad) >> 2); j++)
{
ram[j] = rom[j];
}
/* For the rest of data, copy 1 bytes at per one read */
rom8 = (uint8 *)&(rom[j]);
ram8 = (uint8 *)&(ram[j]);
for (j = 0; j < dataPad; j++)
{
ram8[j] = rom8[j];
}
}

/* Clear zero table */
len = *zeroTable_Ptr;
zeroTable_Ptr++;
zero_layout = (const Sys_ZeroLayoutType *)zeroTable_Ptr;
for(i = 0; i < len; i++)
{
ram = zero_layout[i].ram_start;
size = (uint32)zero_layout[i].ram_end - (uint32)zero_layout[i].ram_start;

for(j = 0UL; j < (size >> 2); j++)
{
ram[j] = 0U;
}
/* Since the size of the section always aligns with 32bits according to the sample file linker.
Zeroing the last 4 bytes of the section if the data to be used of program does not align with 4.*/
if ((size & 0x3U) != 0)
{
ram[j] = 0;
}
}
}

when control reaches to application main function then few of initialized static variable/pointer in RTD files and freeRTOS files that suppose to have some initial value do not have expected values. for example Power_Ip_pxMC_RGM pointer that should point to (0x4028C000u, refer to Power_IM_MC_RGM.c ) is pointing to invalid address causing hard fault.

Please let me knwo if more details are needed.

Thanks

danielmartynek

Hi @AbdNxp,

Sorry for the delay, I was out of office for a few days.

Where is the Power_Ip_pxMC_RGM pointer located in the memory?

AbdNxp

attaching debug screen shots

danielmartynek

Hello @AbdNxp,

It is difficult to find the root cause as this is a sporadic issue.

Can you find Power_Ip_pxMC_RGM in the .map file?

If sometimes Power_Ip_pxMC_RGM is intialized correctly, where is it located in the SRAM, which MPU region?

Can you disable MPU before the jump? The application has a different memmory map and it should initilize the MPU again anyway.

Can you confirm that all the compiler options in your projects match the RTD release notes precisely.

Also, the system clocks must be set precisely to one of the clock options listed in the RM, e.g. Table 151. Option A - High Performance mode (CORE_CLK @ 160 MHz).

Thank you,

BR, Daniel

AbdNxp

Hi @danielmartynek

Its very difficult to track the issue, I was checking if there is any clock issue cause this corruption.

But, after some experiment I am 90% sure, this is not clock issue its any other issue which we are still investigating.

We are creating a new bootloader and test if this helps us.

It would be very helpful if we connect on call.

Thanks & Regards

Abdullah Ansari

danielmartynek

Hello Abdullah,

Our free online technical support does not provide support via calls for many reasons.

I have asked you a few questions here already, can you answer them?

Can you find Power_Ip_pxMC_RGM in the .map file?
If sometimes Power_Ip_pxMC_RGM is intialized correctly, where is the pointer located in the SRAM.
Which MPU region is it?
What are the attributes of the MPU region? Especially the cache configuration.
Have you tried with MPU disabled?
Have you tried using watchpoints at the variables?
Can you confirm that all the compiler options in your projects match the RTD release notes precisely.

Thank you,

Daniel

AbdNxp

the variable is declared in Power_Ip_MC_RGM.c file as below.

static Power_Ip_MC_RGM_Type * Power_Ip_pxMC_RGM = (Power_Ip_MC_RGM_Type *)IP_MC_RGM_BASE;

After bootloader initializes SP,PC and VTOR and jumps to application, then before the main function of application is being called some data from rom to ram is copied as mentioned in below function. If you see below code first initialized data are copied from rom to ram.

void init_data_bss(void)
{
const Sys_CopyLayoutType * copy_layout;
const Sys_ZeroLayoutType * zero_layout;
const uint32 * rom;
const uint8 * rom8;
uint32 * ram;
uint8 * ram8;
uint8 dataPad;
uint32 len = 0U;
uint32 size = 0U;
uint32 i = 0U;
uint32 j = 0U;

const uint32 * initTable_Ptr = (uint32 *)__INIT_TABLE;
const uint32 * zeroTable_Ptr = (uint32*)__ZERO_TABLE;

/* Copy initialized table */
len = *initTable_Ptr;
initTable_Ptr++;
copy_layout = (const Sys_CopyLayoutType *)initTable_Ptr;
for(i = 0; i < len; i++)
{
rom = copy_layout[i].rom_start;
ram = copy_layout[i].ram_start;
size = (uint32)copy_layout[i].rom_end - (uint32)copy_layout[i].rom_start;
/* Make sure the data area to be copied must be aligned with 4. Then, copy 4 bytes at per one read */
dataPad = size & 0x3U;
for(j = 0UL; j < ((size - dataPad) >> 2); j++)
{
ram[j] = rom[j];
}
/* For the rest of data, copy 1 bytes at per one read */
rom8 = (uint8 *)&(rom[j]);
ram8 = (uint8 *)&(ram[j]);
for (j = 0; j < dataPad; j++)
{
ram8[j] = rom8[j];
}
}

/* Clear zero table */
len = *zeroTable_Ptr;
zeroTable_Ptr++;
zero_layout = (const Sys_ZeroLayoutType *)zeroTable_Ptr;
for(i = 0; i < len; i++)
{
ram = zero_layout[i].ram_start;
size = (uint32)zero_layout[i].ram_end - (uint32)zero_layout[i].ram_start;

for(j = 0UL; j < (size >> 2); j++)
{
ram[j] = 0U;
}
/* Since the size of the section always aligns with 32bits according to the sample file linker.
Zeroing the last 4 bytes of the section if the data to be used of program does not align with 4.*/
if ((size & 0x3U) != 0)
{
ram[j] = 0;
}
}
}

My app main function called by main

void AppMain(void)

{

//NOTE : clock and Gpio must be initialized before using

GPIOInit();

WDTInit();

WDTReset();

Power_Ip_Init(&Power_Ip_HwIPsConfigPB); /*power_Ip init, inside this funtion , the variable is used insede this function*/

BoardInit(); /*clock initialization*/

/*

Free Heap before creating task

* This is required because sometimes static variable are not initialized to the constant value

* Its safe to to initialize the static variable by application*/

if ((configTOTAL_HEAP_SIZE - != xPortGetFreeHeapSize())

{

xPortAppInitFreeHeapSize();

}

memset(&gThis, SYS_NULL, sizeof(gThis));

gThis.vStatusLog = &vStatusLog;

if(AppInit() == SYS_SUCCESS)

{

#ifdef SYS_DEBUG_ENABLED

SYS_LOG_INFO("App Init Success");

#end

}

else

{

#ifdef SYS_DEBUG_ENABLED

SYS_LOG_INFO("App Init Failed");

#endif

//todo failure action

}

gThis.nextState = VEHICLE_STATE_LOCKED; //todo: remove after testing

gThis.motorCtrlCANConfig.bit.direction = FORWARD_DIRECTION;

BodyControlSetMotorCtrlEnablePin(SYS_ON);

#ifdef VEHICLE_VARIANT_WITHOUT_TELEMATICS

GPIOWritePin(V4_LDO_DIS_PIN_PORT,V4_LDO_DIS_PIN_PIN, SYS_ON);

GPIOWritePin(LTE_POWER_KEY_PORT,LTE_POWER_KEY_PIN, SYS_OFF);

#elif defined(VEHICLE_VARIANT_ECO_ONLY)

GPIOWritePin(V4_LDO_DIS_PIN_PORT,V4_LDO_DIS_PIN_PIN, SYS_ON);

GPIOWritePin(LTE_POWER_KEY_PORT,LTE_POWER_KEY_PIN, SYS_OFF);

#else

GPIOWritePin(V4_LDO_DIS_PIN_PORT,V4_LDO_DIS_PIN_PIN, SYS_OFF);

#endif

bleInit();

uint8_t retryCount = 10;

do{

WDTReset();

if(OSInit() == SYS_SUCCESS)

{

/*NOTE : Always enable interrupts after intialization

* is completed else unnecessary interrupts causes hurdle in init process due to context switch*/

CANInit(CHANNEL3, (CANRxCompletedCallback *)&CANRxCallback);

IntCtrl_Ip_Init(&IntCtrlConfig_0);

OSStart();

}

else{

retryCount--;

SysDelay(100);

}

} while(retryCount > 0);

while (SYS_TRUE)

{

SysDelay(100000);

}