S32K314 advanced secure boot, JTAG can't connect

[JiayuZhou]

1.S32K314, External oscillator:16M, HSE firmware version:s32k344_hse_fw_0.5.0_2.40.0_pb230807.bin.pink

2.configure utest area: 0x1B000000 and 0x1B000050 already has been configured. DcfClockOption don't configure, because S32K314 have a default value ,meet option A(80M), you can see picture.

3.Then I configure advance secure boot(SMR and CR table), based AES128CMAC algorithm.

4.If I set advance secure boot, after reboot, execute secure boot, it's ok. But If I enable PLL(TempIvt.bootCfgWord |= (IVT_BOOT_CFG_WORD_BOOT_SEQ |IVT_BOOT_CFG_WORD_PLL_ENABLE);) when configuring secure boot, after reboot, code can't run rightly, and S32K314 will reset continuously.

5.we has been test in 8M and 16M External oscillator, the result is same. Of course, the user core we has configured to 160M(HSE only can be configured to 80M[option A]).

Notes:when we use old version HSE firmwire(s32k3x4_hse_fw_0.5.0_2.1.0_pb220625.bin.pink),don't have this question.

this pictures is our utest value when use 16M External oscillator.

[VaneB]

Hi @JiayuZhou 

Could you please share your device's SBAF version (address 0x4039C020) to help rule out any potential issues related to it?

BR, VaneB

[JiayuZhou]

We have been use the latest SBAF version(s32k344_Secure_Baf_0.5.0_0.15.0.6_pb230807.bin.pink)

[VaneB]

Hi @JiayuZhou 

Could you please assist us by sharing an image that shows the memory values of the IVT (Interrupt Vector Table)? This will help us verify the BCW and ensure that the requirements to configure PLL and FXOSC as the HSE clock source during boot are properly fulfilled.

[JiayuZhou]

thank you for answer. Currently,  we have been found the reason. When enable PLL, Because the external 1.5V power supply drive capacity is insufficient, resulting in lower voltage than required, then S32K314 reset. could you confirm that chip will reset when 1.5V lower than required?

[VaneB]

Hi @JiayuZhou 

According to the Hardware Design Guidelines for the S32K3 Microcontrollers, during the power-on sequence, the power supply must ensure a controlled ramp rate from VDD_OFF (0.1V) to the operating voltage levels of VDD_HV_A, VDD_HV_B, and V15. If the ramp rate is not within the specified range, it may lead to unexpected behavior, system malfunctions, or even permanent damage to the MCU.