S32K312 erase D-Flash encounter a problem

[Djd]

Hello NXP team

    Now, I am working with S32K312 and try to erase D-Flash so that can store some data in it, when I config the AIPS_PLAT_CLK to 60Mhz, the erase operation will be ok, but when I changed the AIPS_PLAT_CLK to 40Mhz, the erase operation will return "Program and erase Sequence Error", in other words the MCRS register set the PES bit to 1, but the PEG bit also be set to 1, according to the RM,PEG be set means the erase operation successful, I must set the AIPS_PLAT_CLK to 40Mhz accoring to the work request, please help me solve this problem, I would greatly appreciate it. 

[davidtosenovjan]

Flash module uses AIPS_SLOW_CLK and CORE_CLK. AIPS_SLOW_CLK must always be less than or equal to AIPS_PLAT_CLK. I guess not having these domain in allowed ratio could cause these issues.

Pay attention to clocking options that are allowed to use:

24.7.2 Clocking use case examples