S32K312 PEP error bit of MCRS is set despite of fact that PFCBLK0_SPELOCK, PFCBLK0_SSPELOCK cleared

[Andik]

Hi,

I'm trying to program FLASH of S32K312, for now, it's 32 words from address 0x401000 to 0x40107F (nearly start of "Code flash memory 0").

Communication is done via SWD interface, AHB_AP (DAP master #4). Chip is blank.

PFLASH_PFCBLK0_SPELOCK, PFLASH_PFCBLK0_SSPELOCK, PFLASH_PFCBLK0_SETSLOCK are set to 0.

Reading XRDC_HWCFG1_DID gets 0 as domain ID.

PFLASH_PFCPGM_PEADR_L is loaded with address 0x401000.

FLASH_MCRS is written with PES and PEP set to 1 to clear pending errors.

Data are written to DATAX[0]-DATAx[31].

FLASH_MCR is set to MCR_PGM

FLASH_MCR is set to (MCR_PGM or MCR_EHV)

At this point I get FLASH_MCRS = 0x0002C100, meaning PEP bit is set.

I did not find demos with example of protection management in S32DS. Found S32K344 Demo template with FlashInit.c, FlashProgram.c. Also not sure, where are protected areas described according to particular lock register bits.

Any advice?

Thanks.

A.N.

[danielmartynek · Accepted solution]

Hi @Andik,

Regarding the sectors, if you program 0x401000 to 0x40107F, it is the first super sector in PFLASH_PFCBLK0_SSPELOCK[0].

There are two 1024KB blocks on S32K312.

12x64KB sectors (super sectors) in the first 768KB area of every block.

32x8KB sectors in the last 256KB area of every block.

And this is the programming model, please double-check all the steps.

Do you develop a programmer?

If so, you would get better suport as an NXP partner:

https://www.nxp.com/design/design-center/partner-marketplace/partner-onboarding:PARTNER-ENROLL

Regards,

Daniel

[danielmartynek]

Hi Andrej,

Can you read this register?

Thanks,

Daniel

[Andik]

I have to mention, that core is halted, in debug.

[Andik]

Hi Daniel,
content of PRTN0_CORE2_STAT is 0x80000001