[S32K312_EVB] - LPUART0 incorrectly detects a break

[atranzillo93]

Hi,

I'm using S32K312 172-pin EVB and I'm trying to test LPUART peripheral.

I'm using LPUART 0 instance and I mapped:

• UART_TX = PORTB1
• UART_RX = PORTB0

In my test, LIN pin, output of transceiver, is disconnected from Canoe; therefore, I see B0 and B1 pins HIGH all the time.

The steps in my code are:

1. Init clock
2. Reset STAT and CTRL registers 
3. Set Baud Rate (PLAT clock is 40MHz and baud rate is set to 19200 bps (SBR = 0x15B and OSR = 5))
4. Set LPUART TX -> LPUART mode output pin.
5. Set LPUART RX -> LPUART mode input pin.
6. Enable LIN Break Detection (LBKDE = 1)
7. Enable LIN Break Detect interrupt (LBKDIE = 1)
8. Enable transmitter (TE = 1)
9. Enable receiver (RE = 1)

Problem: when enable receiver operation is performed, LBKDIF bit is immediately set without having a break from master.

Can you help me ?

Thank you.

[atranzillo93]

Hi Daniel,

I have tested SDK example (Uart_Example_S32K312) which uses LPUART3 instance by adding the enabling of break circuitry and by calling Uart_AsyncReceive() API in main and I have seen the same problem.

When RE is set to 1, LBKDIF is immediately set, even if RX and TX lines are floating.

What am I doing wrong?

Best regards,

Anna

[danielmartynek]

Hi Anna,

I have tested the example but I can't reproduce it when PTD3 UART_RX is connected to VDD.

After the Uart_Init(), I write the registers with the debugger.

1. LBKDE = 1
2. LBKDIE = 1
3. RE = 1, LBKDIF still 0.

Can you connect PTD3 to VDD?

Thanks,

BR, Daniel

[atranzillo93]

Hi Daniel,

I have found the problem of break interrupt without LIN connection and it is because I haven't configured IMCR register for LPUART RX pin.

But now I see another problem:

• break interrupt is correctly handled
• LBKDE is disabled
• RIE bit is set

I expect the bit RDRF is set at the end of stop bit of SYNC frame but the FE (framing error) bit is set.

Do you know if it can be linked to registers configuration?

Thanks a lot.

[danielmartynek]

Hi @atranzillo93,

I'm glad it has been solved.

I assume the SBK bit is handled correctly as the LPUART sends 0xAA as expected.

FE = 1 whenever the next character to be read from Data (DATA) is received with logic 0
detected where a stop bit was expected.

The waveforms you posted, where did you measure that?

Can you take analog measurements of the signal?

Does this happen all the time or sporadically?

Thank you,

BR, Daniel

[danielmartynek]

Hi @atranzillo93,

You mentioned that AIPS_PLAT clock is set to 40MHz.

Seems like you selected your own clock configuration, becasue in

Table 148. Option B - Reduced Speed mode (CORE_CLK @ 120 MHz), AIPS_PLAT is 60MHz.

Table 150. Option D - Low-Speed Run mode (CORE_CLK @ 48 MHz), AIPS_PLAT is 48MHz.

We recommend using one of the clock options, becasue they have been validated, all the clocks should be set to the corresponding values.

If you decide to use your own clock configuration, it must be within the Table 145. System clock frequency limitations.

And the divider ratios between the clocks must follow one of the clock options mentioned above.

Below table 145, you can read:

If the clocks do not follow the restrictions, we can't guarantee the specified functionality of the MCU.

Regards,

Daniel

[atranzillo93]

Hi Daniel,

I have set CORE_CLK to 120MHz, PLAT_CLK = 60MHz and I have tested LPUART0 instance that uses PLAT_CLK but the problem still occurs.

The problem seems to be the enabling of receiver (RE= 1) which sets LBKDIF even if no frames are on RX line.

I have the screenshot of LPAURT0 registers:

• before enabling RE

• after enabled RE

With registers configuration, I hope you can help me to understand the problem.

Best regards,

Anna.