S32K3: Hard Fault Error occurred, If the ISR execution time is more than 65us /100us

[nkarthik]

Hi NXP team,

 We are facing the S32K3: Hard Fault Error occurred, If the ISR execution time is more than 65us.

ISR Period is 100us.Please find attached document for more details.

Thanks&Regards

Karthik.N

[danielmartynek]

Hello Karthik,

There seems to be a couple of issues.

First of all, is the exception caused by the MPU?
In the exception handler, if you read the Configurable Fault Status Register (CFSR[MMFSR]), which of the errors do you see there?

https://developer.arm.com/documentation/107706/0100/System-exceptions/Fault-exceptions-and-their-cau...

I see you configure the MPU in the application using RTD MCAL.
Is the MPU configured in the startup code too, or is the MPU disabled there?

Thank you,

Best regards,
Daniel

[nkarthik]

hi ,

1.The issue is not caused by MPU.MPU is disabled both in Startup and Platform.

2.CFSR Register is 0x0

Please let me know if any other possible cause for this issue.

[danielmartynek]

Hello @nkarthik,

You said that you see Hard Fault exception there.

So, in the handler, you should see the type of the exception in CFSR.

Refer to these documents:

https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Handling-Interrupt-DS3-5-...

https://community.nxp.com/t5/S32K-Knowledge-Base/How-To-Debug-A-Fault-Exception-On-ARM-Cortex-M-V7M-...

https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447

The stack corruption can be caused by by several reasons, for example:

• Insufficient stack size,
• Access to unimplemented memory,
• Invalid pointers,
• Unaligned memory accesses or MPU misconfiguration,
• Cache coherency

Recomended debugging:

• Analyze the fault exception.
• Check stack usage - for example by initializing the SRAM with a known pattern that gets overwritten.
• Increase the Stack size
• Try with Cache disabled
• Check the MPU configuration - It is importatnt to know exactly what are the attribites of each region.
• Review interrupt priority
• Review the errata: https://www.nxp.com/webapp/Download?colCode=S32K342_0P97C

Regards,

Daniel