S32K3_ADC_Channcal_configure_problem

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S32K3_ADC_Channcal_configure_problem

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wuxianlong
Contributor III

Using the ADC configured by S32K312, due to the large number of channels, some special pins are used. Some problems are encountered during use. The pin configuration does not take effect, and the ADC channel does not get correct data. I use the normal sampling mode. SW RTD2.0.0.

The first one: One ADC channel corresponds to multiple pins, such as s_in, 8. I checked PTA0 and used the PTA0 channel to collect the level, but the ADC sampling value of the 8-channel I read is incorrect. I still need to configure what?
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The second: like s_in, 23 s_in,22. I want to use the ADC to collect the PTD28 voltage, but my configuration does not take effect, and the voltage value of the PTD28 cannot be obtained. The system default is PTE17 and cannot be cancelled.
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The third; is to configure the external input ADC, such as ADC0_X[1] I don't see much description in the RM manual, where should I go to get more information.
my configure

wuxianlong_0-1664122935380.png

 

 

 

 

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Robin_Shen
NXP TechSupport
NXP TechSupport

You are correct. Siul2_Port_Ip_Init() enables the ADC related bits in DCMRWF4 register by default. The RTD LLD version is SW32K3_RTD_4.4_2.0.0_DS_updatesite_D2204 and the running environment is S32 Design Studio IDE v3.4 Update 3.

It was reported several days ago. And the Proposed solution is what you did(Change the default "|" to "&" in Siul2_Port_Ip_WriteDCMConfiguration() API).

Sorry for the inconvenience we bring you!

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi wuxianlong,

Q1\Q2: You can refer to the discussion in S32K344 ADC coversion result jump problem

DCMRWF4[MUX_MODE_EN_ADC1_S22][MUX_MODE_EN_ADC0_S8].pngS32K312_IOMUX ADC0_S8 ADC1_S22.png

Q3:Each ADC provides 3 external decode signals (MA) to be used to select 1 channel out of 8 in the external analog multiplexers.

58.3.12 External decode signals delay.png

The decoding signals for the selection of external ADC channels (ADC_X) are gray-encoded.Table 283. ADC channel mapping.png


Best Regards,
Robin

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wuxianlong
Contributor III

@Robin_Shen 

before port init, 

DCM_DCMRWF4 = 1,

 

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wuxianlong
Contributor III

sorry   
before   port  init ,
DCM_DCMRWF4 = 0;

after port init ,
DCM_DCMRWF4 = 1;

And, i change  the port select ,DCM_DCMRWF4 = 1 still.

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wuxianlong
Contributor III

Hi,@Robin_Shen 

I wonder if the code needs to be modified.
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Robin_Shen
NXP TechSupport
NXP TechSupport

You are correct. Siul2_Port_Ip_Init() enables the ADC related bits in DCMRWF4 register by default. The RTD LLD version is SW32K3_RTD_4.4_2.0.0_DS_updatesite_D2204 and the running environment is S32 Design Studio IDE v3.4 Update 3.

It was reported several days ago. And the Proposed solution is what you did(Change the default "|" to "&" in Siul2_Port_Ip_WriteDCMConfiguration() API).

Sorry for the inconvenience we bring you!

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gumu
Contributor IV

Hi @Robin_Shen,

We also have the same issue in our project.

I'd like to konw which RTD package can fix this issue.

Thanks!

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wuxianlong
Contributor III

@Robin_Shenhi,

I verify the method of modifying the code, which seems feasible. Can you confirm it. If it is convenient, can you give me your contact information?

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wuxianlong
Contributor III

Hi,@Robin_Shen
Thank you for your help,
1、According to the description of the manual, the default value should be 0. No matter how configured the S8 channel is, it is 1, is it that I have not configured it successfully? I checked the code of RTD2.0.0 and found that the register change code is not running.
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2、about the email

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