S32K1xx SPI Slave: Is it possible to get PCS interrupt to setup sending data before start SCK?

[Nishida]

Questions:

Is it possible to get PCS interrupt to setup send data before start SCK?

Background:

I am implementing SPI slave device using S32K142.

Slave device must send latest data to Master device at the moment (It means latest data), threfore I need to know timing when master requests data (It means start of frame, at PCS asserted).

If software can detect timing when PCS asserted by interrupt, it can prepere data to be sent to the master device before SCK (Clock) start.

I already checked LPSPI section of S32K 142 manual, and there is no interrupt to get PCS asserted (Start of frame).

Therefore, I want to know whether I can get PCS pin interrupt like GPIO even if PCS pin is still configured to LPSPI. If to catch the interrupt is possible, I want to call SPI driver in the interrupt handler. 

Note) Hardware change is not possible.

[danielmartynek]

Hi @Nishida,

The problem is that the transmit FIFO must be filled with transmit data before the LPSPI_PCS input asserts.

You can use the Transmit Data Flag (TDF) and fill the FIFO whenever the number of words drops below the TX Watermark.

Regards,

Daniel

[Nishida]

@danielmartynek 

Thankyou for the replay.

I have additional questions.

 - Even though, can we get PCS interrupt?
 - Could you please explain your idea how to use Transmit Data Flag (TDF) in the situation?

[danielmartynek]

Hi @Nishida,

The TDF flag is set, whenever the number of words in the transmit FIFO drops below a certain level (TXWATER). That means that there is a room in the FIFO for new data.

But this is really application dependent.

You can use another signal from the master to indicate the master is going to read data.

Or you can send a command via SPI to get the slave ready...

Regarding the PCS interrupt, the LPSPI module does not feature that.

But the PORT module can generate interrupts on pins that are used in digital modes (like LPSPI_PCS). Please refer to the S32K1xx RM rev.13, Section 12.6.4 External interrupts

Regards,

Daniel