S32K148 hangs up during wake up from VLPS

[pengcheng_wang]

Hi,

MCAL is used.

Go  to VLPS mode from Run mode and waked up by GPIO D & E interrupt. Both GPIO and NVIC interrupt are enabled and other interrupts are disabled. The wake up source interrupt is not the highest priority. After wakeup Mcu_PerformReset is called immediately to perform system reset. But it hangs up sometimes and It's hard to reproduce. Make sure that the clock setting meets the ERR011063 mentioned in errata.

S32K148 can be attached by PE when this issue happens. I'm not sure it hangs up during exit VLPS mode or perform system reset. 

Does anyone have some suggestions?

Thank you

BR

[danielmartynek]

Hi pengcheng.wang@harman.com,

You could enabled BUC_CLK on a CLKOUT pin and scope the signal along with the GPIO wakeup signals.

In VLPS, the BUS_CLK is gated off.

But if you can connected the PE debugger to the MCU in an attach session without resetting the MCU (that is what I understand from the description above), you should be able to halt the execution and examine the state of the MCU.

Regards,

Daniel

[pengcheng_wang]

Hello Daniel,

Some resigters are dumped when PE is connected. please find them below.

some phenomena are very strange,

1. why internal watchdog does NOT reset the system after the LPIT interrupt which is used by MCAL to feed the watchdog is disabled before switching to VLPS?
2. why S32K seems hang up in the wakeup source ISR?

--------------------------------------------------------------

WDOG:

CS: 0x000035A0 @40052000
CNT: 0x00000002 @40052004
TOVAL: 0x000000FA @40052008
WIN: 0x00000000 @4005200c

SCG:

VERID: 0x01000000 @40064000
PARAM: 0xD800004E @40064004
CSR: 0x02010013 @40064010
RCCR: 0x02010013 @40064014
VCCR: 0x02010003 @40064018
HCCR: 0x06010033 @4006401c
CLKOUTCNFG: 0x01000000 @40064020
SOSCCSR: 0x00000000 @40064100
SOSCDIV: 0x00000103 @40064104
SOSCCFG: 0x00000034 @40064108
SIRCCSR: 0x03000003 @40064200
SIRCDIV: 0x00000202 @40064204
SIRCCFG: 0x00000001 @40064208
FIRCCSR: 0x00000008 @40064300
FIRCDIV: 0x00000201 @40064304
FIRCCFG: 0x00000000 @40064308
SPLLCSR: 0x00000000 @40064600
SPLLDIV: 0x00000302 @40064604
SPLLCFG: 0x00040000 @40064608

SMC：

VERID: 0x01000000 @4007e000
PARAM: 0x00000001 @4007e004
PMPROT: 0x000000A0 @4007e008
PMCTRL: 0x0000000A @4007e00c
STOPCTRL: 0x00000003 @4007e010
PMSTAT: 0x00000001 @4007e014

SCB:

ACTLR: 0x00000000 @e000e008
CPUID: 0x410FC241 @e000ed00
ICSR: 0x0044F000 @e000ed04
VTOR: 0x00089000 @e000ed08
AIRCR: 0xFA050000 @e000ed0c
SCR: 0x00000004 @e000ed10
CCR: 0x00000201 @e000ed14
SHPR1: 0x00000000 @e000ed18
SHPR2: 0x00000000 @e000ed1c
SHPR3: 0x20000000 @e000ed20
SHCSR: 0x00070000 @e000ed24
CFSR: 0x00000000 @e000ed28
HFSR: 0x00000000 @e000ed2c
DFSR: 0x0000000B @e000ed30
MMFAR: 0xE000EDF8 @e000ed34
BFAR: 0xE000EDF8 @e000ed38
AFSR: 0x00000000 @e000ed3c
CPACR: 0x00000000 @e000ed88
FPCCR: 0xC0000000 @e000ef34
FPCAR: 0x00000000 @e000ef38
FPDSCR: 0x00000000 @e000ef3c

[danielmartynek]

Hello pengcheng.wang@harman.com,

For some reason PMCTRL_VLPSA = 1, the previous stop mode entry was aborted.
Can you read the flag after each transition to VLPS?

Regarding the WDOG, if the counter is not incrementing, please check if the WDOG clock (LPO based on the WDOG_CS value) is enabled.

I see that PORTE interrupt was pending ICSR[VECTPENDING] = 79 (0x4F) but there was no active interrupt at the time you read the registers ICSR[VECTACTIVE] = 0.
And even if it was stuck in an ISR, does it mean you cannot clear the corresponding flag?
Is the port configured for a level sensitive interrupt or an edge sensitive interrupt?

BR, Daniel

[pengcheng_wang]

Hello Daniel,

Regarding the WDOG, if the counter is not incrementing, please check if the WDOG clock (LPO based on the WDOG_CS value) is enabled.

   -> LPO is enabled.

   -> REGSC: 0x45 @4007d002

I see that PORTE interrupt was pending ICSR[VECTPENDING] = 79 (0x4F) but there was no active interrupt at the time you read the registers ICSR[VECTACTIVE] = 0.
And even if it was stuck in an ISR, does it mean you cannot clear the corresponding flag?

   ->PORTE interrupt is Autosar CAT2 interrupt. Active flag will be cleared by Autosar OS service.

Is the port configured for a level sensitive interrupt or an edge sensitive interrupt?

   ->level sensitive

[danielmartynek]

Hello pengcheng.wang@harman.com,

So is the WDOG_CNT incrementing?

It increments rather slowly as the clock source is LPO with the 256 prescaler enabled and the WDOg is not running in Debug mode.

REGSC is not the right register to look at but LPOCLKS.

Is it possible that sometimes the PORTE input signal remains asserted?

Regards,

Daniel

[pengcheng_wang]

Hi Daniel,

I don't think the WDOG_CNT is incrementing. Because when this issue happens, without doing anything include connecting PE, it can not be recovered so i think watchdog does not work in this case.

which is the right register?

In wakeup source ISR, software reset is performed so it doesn't matter even the pin remains asserted.

[danielmartynek]

Hi,

This is a very strange issue, had to say what could be wrong.

But since you can dump the registers, you should be able to step the code and see what exactly it does.

Which version of MCAL do you use?

As I already mentioned, the interrupt is pending but not active (at least at the time you read the registers).

Can you please read PRIMASK, BASEPRI and NVIC configuration?

You can enable WDOG in Debug mode (CS_DBG = 1), just to test it.

The LPO clock must be enabled in LPOCLKS, you can also test it externally on a CLKOUT pin.

Thanks,

BR, Daniel

[pengcheng_wang]

Hi Daniel,

Thank you for your support.

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