S32K148 SPI transferred issue with SDK 4.0.3

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S32K148 SPI transferred issue with SDK 4.0.3

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Leon06
Contributor III

Hi All,

I use S32K148 and SDK 4.0.3 to control other SPI slaves.

Below is the data transferred with SPI.

Ch0 : SPI CS

Ch1 : SPI MISO

Ch2 : SPI MOSI

CH3 : CLOCK

CH4 : For debugging, I/O toggles before SPI doing transferred

In the normal mode, Ch4 toggled before the SPI transferred data.

Leon06_0-1684906571711.png

In some cases, the SPI transfers one more data after the correct data transferred, but the toggle pin does not toggle before.

未命名.png

 

 

 

 

 

 

 

 

 

After that, SPI is stalled and doesn't  transfers data again.

Also, the SPI Status is keeping in busy mode.

Leon06_1-1684907149473.png

How could I do to fixing this issue to make SPI working normally?

Leon

 

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danielmartynek
NXP TechSupport
NXP TechSupport

You can change it to SAMPLE = 0.

This loopback feature (SAMPLE = 1) is implemented on LPSPI0 and on PTD15 and PTE0 only.

The CFGR1[1] SAMPLE bit improves the setup time of the input data from the slave (MISO signal).

Becasue if SAMPLE = 1 the Master does not sample the internal SCK signal but the actual SCK signal on the bus.

danielmartynek_0-1685695260890.png

 

This is useful at higher baudrates.

tSU: Data setup time(inputs) is specified in the DS, Table 46. LPSPI electrical specifications (NUM 6).

tSU min 29ns (SAMPLE = 0, at 5V, RUN)

tSU min 7ns (SAMPLE = 1, at 5V, RUN)

 

 

Regards,

Daniel

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @Leon06,

Do you use interrupt or DMA mode?

Is there any error feedback event, or do the APIs return any error status codes?

Can you share the project so that I can test it on my side?

 

Regards,

Daniel

 

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Leon06
Contributor III

Hi Daniel,

I use the the SPI configuration as below setting.

/*! @brief SPI_PAL instance */
spi_instance_t spi1Instance =
{
    .instType = SPI_INST_TYPE_LPSPI,
    .instIdx = 1U
};

/* SPI Master Configurations */
spi_master_t MasterConfig0 =
{
    .baudRate      = 250000U,
    .ssPolarity    = SPI_ACTIVE_LOW,
    .frameSize     = 16U,
    .clockPhase    = READ_ON_EVEN_EDGE,
    .clockPolarity = SPI_ACTIVE_LOW,
    .bitOrder      = SPI_TRANSFER_MSB_FIRST,
    .transferType  = SPI_USING_DMA,
    .rxDMAChannel  = 0U,
    .txDMAChannel  = 1U,
    .callback      = NULL,
    .callbackParam = NULL,
    .ssPin         = 3,
    .extension     = NULL
};

Once the fault exits, the bit24 of the SPI SR (Status Register) is 1, indicating that the SPI channel is keeping in busy status.

Leon06_0-1684976946440.png

Leon06_1-1684977764093.png

I am using the DMA triggered by LPIT every 2ms  about SPI Tx data.

 

Leon

 

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danielmartynek
NXP TechSupport
NXP TechSupport

HI Leon,

Since the GPIO stops toggling, it must be stuck somewhere.

Do you see any DMA error?

If you don't want to share the project here, you can create a ticket.

 

Regards,

Daniel

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Leon06
Contributor III

Hi Daniel,

These days, I continued working on solving this case.

I checked the dma status, no error occured.

Leon06_2-1685599188686.png

 

I found if there are some noises on the SPI clock, it could easily make the SPI transferred error.

Below is the SPI signal monitored by the logic analyzer. I have noticed a 2ns clock noise on the SPI clock signal, which could potentially cause errors during data transfer.

Leon06_0-1685589443091.png

If the clock noise continuously exists, the SPI error would easily occur.

 

I'm still confused as to why the SPI successfully transfers the data frame, the CS pin returns to high, but then the CS pin goes low again and the transfer of another data frame fails, resulting in the SPI channel being stalled. It's quite strange.

Leon06_1-1685599043860.png

Leon06_0-1685598984692.png

I'm sorry for I couldn't share the project because of our company's policy.

How could I share the enough informations for solving this case?

Thanks.

Leon

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @Leon06,

Regarding the noise on the SCK line, it can impact the transceiver if CFGR1[SAMPLE] = 1.

Otherwise the LPSPI sees the internal SCK signal only.

danielmartynek_0-1685608516793.png

 

Is SAMPLE set in the project?

 

Thanks,

BR, Daniel

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Leon06
Contributor III

Hi Daniel,

Below is the SPI channel register.

Leon06_0-1685611109116.png

What should I set this register?

Regards,

Leon

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danielmartynek
NXP TechSupport
NXP TechSupport

Can you try with 0x0000_0001?

Thank you

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Leon06
Contributor III

Hi @danielmartynek ,

Thanks for your suggestion, I changed the value to CFGR1[SAMPLE] = 0x0000 0001.

For now, it's working.

But I check the SDK 4.0.3 lpspi_master_driver.c, the function

status_t LPSPI_DRV_MasterConfigureBus(uint32_t instance,const lpspi_master_config_t * spiConfig,
uint32_t * calculatedBaudRate) is always setting the CFGR1 Bit1 = true.

Leon06_0-1685670853447.png 

So should I change line374 to LPSPI_SetSamplingPoint(base, false);? If I make this change, will it cause any other proplems?

 

Regards,

Leon

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danielmartynek
NXP TechSupport
NXP TechSupport

You can change it to SAMPLE = 0.

This loopback feature (SAMPLE = 1) is implemented on LPSPI0 and on PTD15 and PTE0 only.

The CFGR1[1] SAMPLE bit improves the setup time of the input data from the slave (MISO signal).

Becasue if SAMPLE = 1 the Master does not sample the internal SCK signal but the actual SCK signal on the bus.

danielmartynek_0-1685695260890.png

 

This is useful at higher baudrates.

tSU: Data setup time(inputs) is specified in the DS, Table 46. LPSPI electrical specifications (NUM 6).

tSU min 29ns (SAMPLE = 0, at 5V, RUN)

tSU min 7ns (SAMPLE = 1, at 5V, RUN)

 

 

Regards,

Daniel

 

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