I'm using SPI slave on a S32K148EVB board.
My code is based on the spi_pal demo.
For master part I'm using either:
- (1) S32K148EVB with spi_pal demo
- (2) S32K148EVB with lpspi_dma demo
- (3) Raspberry PI
here is my slave configuration:
The slave behavior is correct with the master (1) and (2) but when using master (3) the MISO pin is not in the good state when the clock starts, resulting in bit shifts.
In the case of master (3) the SS pin is enabled (low) 11.8µs before the clock starts:
And the MISO pin doesn't go LOW after SS pin is enabled.
At first clock falling edge, the MISO pin is not correct.
In case of master (1) and (2) the MISO pin behavior is like this:
At first clock falling edge, the MISO pin is correct.
is there any reason why the MISO pin will not go LOW when SS pin is enabled?
the baudrate I'm using is different, for master (3) I'm using 5M and for (1) and (2) I tried 1M maximum, but I don't believe it should make a difference for MISO pin.
We found the solution by changing the slave configuration of "Phase" to "Read on second edge".
We also changed the configuration of master (3) to adapt to this configuration.