S32K148 - SAI bitclock slave and polarity

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S32K148 - SAI bitclock slave and polarity

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jakub_mielczare
Contributor III

Hello,

In my application I need to use SAI0 in bitclock slave mode (bitclock externally generated).

Attached is the relation between external bitclock and external frame sync.

When I configure SAI0 transmitter with bitclock active LOW, it works fine. SAI0 transmits data on falling edge of bitclock (is this right?).

When I configure SAI0 transmitter with bitclock active HIGH, it does not start to transmit at all. Should it work with the attached signals? If not, what should be changed?

Best regards,

Jakub

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello Jakub,

I'm sorry for the late response.

Do you have still the issue?

If so, could you please provide more information about the configuration?

Could you attach a test project?

Are you using your own implementation or the SDK driver?

Have you reproduced this behavior with the SDK driver?

Thank you,

BR, Daniel

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jakub_mielczare
Contributor III

Hello Daniel,

I still have this issue. It is with our driver. I did not try SDK project or driver.

I don't have a project which I can share. I can provide register dump if needed.

Could it be that MCU expects DSP standard signals (BCLK and FS) while the attached are according to I2S standard as described in NXP AN12202?

Best regards,

Jakub

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello Jakub,

Please share the registers and, if possible, capture all the signals zoomed-out on both Bit Clock polarities.

Thank you,

BR, Daniel

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jakub_mielczare
Contributor III

Hello Daniel,

Please find attached SAI0 register dumps for bitclock active low and high respectively. Attaching also signal traces for both cases, zoomed in and out.

Channel 0 : bitclock

Channel 1-4 : data

Channel 5 : frame sync

Best regards,

Jakub

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello Jakub,

Thank you for all the information.

I used your slave configuration and emulated the master using a PWM signal and a GPIO - to keep it simple - based on the captured signals you sent.

I'm able to reproduce this behavior because the frame sync in your application can be sampled on the rising edge of BCLK

pastedImage_1.png

which is correct when BCP = 1.

pastedImage_2.png

When BCP = 0, the frame sync signal is being sampled on the falling edge of BCLK as shown below.

pastedImage_3.png 

pastedImage_2.png

BR, Daniel

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jakub_mielczare
Contributor III

Hi Daniel,

Thank you. Can anything be done to have it working (in the email notification I got information that making the FS longer could help, but I don't see this in the post)?

Best regards,

Jakub

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Jakub,

I meant that the slave can't see the FS because the FS is just one BCLK period long and can be sampled on the rising edge of BCLK only. Can you reconfigure the master to send the FS signal on the rising edge of BCLK so that the slave can sample the signal on the falling edge of BCLK.

Regards,

Daniel 

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jakub_mielczare
Contributor III

Hi Daniel,

Thank you. I will try it. Currently we have re-configured our TDM to bitclock active LOW.

Best regards,

Jakub

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