S32K148 QSPI clock settings issue

[Konrad_M]

Hi.
I work with EVB and using QSPI example from S32 Design Studio. Goal: SCLK = 80MHz
Using PLL_DIV1 and various settings max 20Mhz works.
Default project settings use FIRC and divider set to 4. 
Has anyone tried to change QSPI frequency in this example? 

Any ideas? 

[Konrad_M]

Using PLL, as shown, even 30MHz is too much....program stops and wait forever on last RX interrupt

[Robin_Shen]

Hi Konrad_M,

Sorry for my last reply.
I confused the QSPI and LSPI routines.
After modify the S32K148EVB circuit and change the clock configuration, I encountered the same phenomenon you described.

According to the description of the Data Sheet "Table 39. QuadSPI electrical specifications", the max SCK Clock Frequency of FLASH A PORT should be 38MHz when Internal Sampling is selected.

I got their feedback after consulting the AE team:

I re-appeared the issue you describled. After anslysis, this issue is not caused by the clock frequency. when you read data and the size is larger than 256 bytes, it will happen the overflow error. so it will pending in that line. if I reallocated the read API into the write process, which read 256 bytes every time, it work well. That means the maximum clock frequency can reach 38MHz. about the overflow error, I will test it in the newest version. if still exist, I will create a ticket in our system.

Best Regards,
Robin
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[Robin_Shen]

Hi Konrad_M,

Maybe you can refer the method shown below:

Best Regards,
Robin
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[yihe_zuo]

Can SPLLDIV2_CLK be set with 80Mhz?

I checked the datasheet it should be less than the one in the below?

Could you double check?

[Konrad_M]

Good point but didn't help.
SPLLDIV2_CLK should be 40Mhz or less but QSPI uses SPLLDIV1_CLK.
Thank you.