S32K148 CAN Bus-off recovery

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S32K148 CAN Bus-off recovery

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Contributor III

Hello,

When I initially setup FlexCAN peripheral for non-FD function, my S32K148 unit works as intended, it receives CAN messages from other participants and transmits its own messages. However, when I put the MCU to sleep and wake it up again, I get stuck in a bus off state and can't recover.

This is how I deinitialize the  FlexCAN peripheral before putting the MCU to sleep:

// 1. Switch the FlexCAN to FREEZE mode and deactivate it.
CAN0->MCR |= CAN_MCR_FRZ(1U) | CAN_MCR_HALT(1U);
if ((CAN0->MCR & CAN_MCR_MDIS_MASK) != 0x0)
{
   CAN0->MCR &= ~CAN_MCR_MDIS_MASK;
}
while ((CAN0->MCR & CAN_MCR_FRZACK_MASK) == 0x0) { ; }

// 2. Disconnect clock source.

PCC->PCCn[PCC_FlexCAN0_INDEX] &= ~PCC_PCCn_CGC_MASK;

I put the MCU to sleep mode using asm("WFI");

When the wake up condition occours, the MCU wakes up correctly, I jump at the beginning of the main function in order to  initialize all peripherals in the same way, but the CAN0 module gets stuck in bus off state. I checked the values of control registers of the CAN0 module after the first initialization and after the wakeup initialization. All values are the same except for:

ECR - after the first initialization, the counters are all zeroed, after wakeup it shows non zero value of the RXERRCNT, which increases after I continue the debug session, but never keeps a constant value.

ESR1 - after the first initialization also zeroed, after wakeup it shows ERRINT = 1.

ESR2 - after first initialization IMB = 1, after wakeup, both IMB and VPS = 1.

I have the automatic bus off recovery option enabled in the CTRL1 register and don't try to transmit any messages when the bus off state is active. But unfortunately, I never leave the bus off state, only after resetting the MCU, which causes loss of data.

Thanks for advice!

Tomas

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5 Replies

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NXP TechSupport
NXP TechSupport

Hi Tomas,

you should not disable module clock when module is enabled, so if you want to gate off the clock using PCC, put FlexCAN into Module disable mode (enter Freeze then clear MDIS and poll LPMACK, as chapter 55.1.9.2 of the RM suggests).

Regarding bus off; the description does not indicate bus off is entered. You should see BOFFINT flag set and TXERROR counter increased, then cleared and so on. Thus it can points to some clock issue or wrong bit timing.

BR, Petr 

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Contributor III

I tried to modify my reply, but the page shunt me as apparently I can only make modifications in a limited time window 

Anyway, this is how I disable the CAN module:

// 1. Switch module to FREEZE mode.
((CAN0->MCR |= CAN_MCR_FRZ(1U) | CAN_MCR_HALT(1U);
if ((CAN0->MCR & CAN_MCR_MDIS_MASK) != 0x0)
{
        CAN0->MCR &= ~CAN_MCR_MDIS_MASK;
}
while ((CAN0->MCR & CAN_MCR_FRZACK_MASK) == 0x0) { ; }
			
// 2. Deactivate the module.
CAN0->MCR |= CAN_MCR_MDIS(1U);
while ((CAN0->MCR & CAN_MCR_LPMACK_MASK) == 0x0) { ; }

// 3. Disconnect the clock.
PCC->PCCn[PCC_FlexCAN0_INDEX] &= ~PCC_PCCn_CGC_MASK;
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Contributor III

Hello, Petr,

thank you for you reply and sorry for the delay.

When disabling the CAN module, I am proceeding exactly as you describe, as seen in my original question. 1. Entering Freeze mode 2. Disabling module and polling the LPMACK 3. Disconnecting clock in PCC. Disconnecting the clock first, than modifying the control registers would result in a HardFault anyway. 

After wakeup, I can see exactly the conditions you describe for bus off status. BOFFINT is set and TXERRCNT is increasing. I'm attaching screenshots from Keil debug session.

Tomas

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NXP TechSupport
NXP TechSupport

Hi Tomas,

 

is there any message transmitted upon wake up? Check bus signal. Check correct bitrate generated on TX pin.

If nothing should be transmitted before you get in to Bus off check MB area for correct values.

Anyway it points for bit timing issue, wrong config or different PE clock

 

BR, Petr 

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Contributor III

Hello, Petr,

Sorry for a hasty question, I just found the source of my problem. Both CAN module and clock were configured correctly, but in our ECU we also use UJA113 System base chip as voltage regulator and CAN driver. When entering the VLPS, I configure the SBC to shut down voltage regulator for other peripheries (not the MCU) and CAN transciever, but after wakeup I forgot to tell the SBC to activate the transciever and V2 again. As a result, there was no traffic on the SBC-MCU CAN Rx line and Tx entered busoff because of the missing ACK signals.

Thank you for your time!

Tomas

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