S32K146 How to Tristate UART TxD Pin

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S32K146 How to Tristate UART TxD Pin

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danielreinwald
Contributor II

I'm trying to work on a serial bus with more then one member connected to the same Tx output line.

Regarding to the reference manual of the S32K the TXD pin is tristated after the transmitter has completed his activity and the TE bit  of the LPUART CTRL register is cleared.

This is not working in my application. Is there another register setting i have to consider to get the TXD pin into tristate mode after completed activity?

I added my configuration of the Lpuart Module and my Transmission ISR below.

void Configure_UartPorts(void)
{
    PCC->PCCn[PCC_PORTC_INDEX] |= PCC_PCCn_CGC_MASK;    /* Enable clock for PORTC */
    
    PORTC->PCR[2] |= PORT_PCR_MUX(4);                    /* Port C2, ALT4 MUX = UART_RX0 */
    PORTC->PCR[3] |= PORT_PCR_MUX(4);                    /* Port C3, ALT4 MUX = UART_TX0 */

    PORTC->PCR[6] |= PORT_PCR_MUX(2);                    /* Port C6, ALT2 MUX = UART_RX1 */
    PORTC->PCR[7] |= PORT_PCR_MUX(2);                    /* Port C7, ALT2 MUX = UART_TX1 */
}

void LPUART1_Module_Init(void)
{
    //***** Configuration of PCC clock source of LPUART0 *****//
    PCC->PCCn[PCC_LPUART1_INDEX] &= ~PCC_PCCn_CGC_MASK;       /* Disabled clock for config of LPUART 1*/
    PCC->PCCn[PCC_LPUART1_INDEX] |= PCC_PCCn_PCS(6)                    /* PCS = 6: clock source is S                                                                                                                                  SPLL2DIV2_CLK (40 MHz) */

   |  PCC_PCCn_CGC_MASK;                                                                           /* enable clock for LPUART 1*/

    //***** Configuration of LPUART1 values and characteristics *****//
    LPUART1->BAUD = 0x0F00002B;                                /* OSR = 15: over sampling rate = 15 + 1 = 16 */
                                                                                           /* SBNS = 1: 1 stop bits */
                                                                                           /* SBR = 24 (0x17): BAUDRATE = BAUDCLOCK / ((OSR + 1)                                                                                               x BAUDRATEDIVISOR) */
                                                                                           /* BAUDRATEDIVISOR = BAUDCLOCK / BAUDRATE / OSR =                                                                                               40000000 / 57600 / 16 = ~43 */
    LPUART1->CTRL = 0x002C0000;                                 /* RIE = 1, TIE = 0: Receive interrupt enable, transmission                                                                                                interrupt disable */
                                                                                            /* TE = 1, RE = 1: Transmitter enable, Receiver enabled */

    //***** LPUART0 *****//
    S32_NVIC->ICPR[1] = 1 << (33 % 32);                          /* IRQ33-LPUART1 RxTx: clr any pending IRQ */
    S32_NVIC->ISER[1] = 1 << (33 % 32);                          /* IRQ33-LPUART1 RxTx: enable IRQ */
    S32_NVIC->IP[33] = 0x02;                                             /* IRQ33-LPUART1 RxTx: priority 2 of 0-15 */
    LPUART1->STAT |= LPUART_STAT_RXEDGIF(0);      /* Clear Rising Edge Rx Interrupt (löst sonst dauerhaft einen                                                                                                IRQ aus) */

    AEC_RxFifo = (Fifo_t*) Fifo_Create(Aec_BufferRx, AECBUFFRX, sizeof(uint8_t));
    AEC_TxFifo = (Fifo_t*) Fifo_Create(Aec_BufferTx, AECBUFFTX, sizeof(uint8_t));

    Init_IntStruct(&Aec_Commands);
}


/*!******************************************************************************************
*  @Function:  LPUART1_RxTx_IRQHandler()
* ------------------------------------------------------------------------------------------
*  @ISR with callback on stand alone Rx- and Tx- ISR function
* ------------------------------------------------------------------------------------------
*  @Input-Parameter     -
*
*  @Output-Parameter    -
* ------------------------------------------------------------------------------------------
*  @Revision        By            Functional improvement
*  @24.06.2019      D.R.
********************************************************************************************/

void LPUART1_RxTx_IRQHandler(void)
{
    //***** Check receive data buffer *****//
    if((LPUART1->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT)
    {
        LPUART1_RxISR();
    }

    //***** Check transmit data buffer *****//
    if((LPUART1->CTRL & LPUART_CTRL_TIE_MASK) >> LPUART_CTRL_TIE_SHIFT)
    {
        if((LPUART1->STAT & LPUART_STAT_TDRE_MASK) >> LPUART_STAT_TDRE_SHIFT)
        {
            LPUART1_TxISR();
        }
    }
}


void LPUART1_TxISR(void)                       
{
    if(false == Fifo_Empty(AEC_TxFifo))
    {
        LPUART1->DATA = Fifo_ReadByte(AEC_TxFifo);
    }
    else
    {
        LPUART1->CTRL &= ~ LPUART_CTRL_TIE_MASK;
        LPUART1->CTRL &= ~ LPUART_CTRL_TE_MASK;
    }
}

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danielreinwald
Contributor II

Hi Alexis,

i tried to disable it outside the interruption, but it's still not working as expected.

After some reasearch with the oscilloscope, i found out that the UART Tx pin goes out of the tristate mode after changing his multiplexer state to UART. The UART transmitter in the CTRL Register is still disabled.

PORTC->PCR[7] |= PORT_PCR_MUX(2);                    /* Port C7, ALT2 MUX = UART_TX1 */

After deleting the multiplexer, changing his state back to default (GPIO) it goes into tristate again.

PORTC->PCR[7] &= ~ PORT_PCR_MUX(2);                    /* Port C7, ALT2 MUX = UART_TX1 */

I'm at a loss, maybe you have an idea? Deleting the Multiplexer is destroying the last byte in transmission buffer without any delaytime.

Thanks and Best Regards,

Daniel

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Alexis_A
NXP TechSupport
NXP TechSupport

Hi Daniel,

It should be enough to disable this bit, could you try disabling it outside the interruption?

Best Regards,

Alexis Andalon

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