S32K146 FTM trouble

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S32K146 FTM trouble

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o_shantalosov
Contributor I

Hi.

I'm working with S32K146 controller and having trouble with FTM4.

I'm initialize the timer in counter mode and after start CNT register change value from 0 to 65535 in a circle.

Now I want to configure interrupt when CNT register change value from 65535 to 0.

I set TOIE bit in SC register

FTM4->SC |= FTM_SC_TOIE_MASK;

and set interrupt enable in NVIC

S32_NVIC->ISER[FTM4_Ovf_Reload_IRQn / 32] |= (1 << (FTM4_Ovf_Reload_IRQn % 32));

I also add interrupt handler function:

void FTM4_Ovf_Reload_IRQHandler(void)
{
  FTM4->SC &= ~FTM_SC_TOF_MASK;
  return;
}

Vector Table in startup file have corresponding pointer to my handler

.long   FTM4_Ovf_Reload_IRQHandler                      /* FTM4 Counter overflow and Reload interrupt*/

But, CNT register overflow triggered DefaultISR handler.

I stop debugger and see programm stay in DefaultISR function located at 0x1065c in code memory.

At this time register xPSR = 0x21000090. FTM4_Ovf_Reload_IRQHandler  located at 0x0134ad. Vector table offset VTOR = 0x10200. Code memory 0x10440 (corresponding to the interrupt vector 0x90) store word 0x1034AD.

The most intresting, when I change in my code FTM4 to FTM0 or FTM1 the trouble goes away

FTM0 or FTM1 worked nice!

FTM2-FTM5 dotn work.

Why? Help me!

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o_shantalosov
Contributor I

Hi Daniel, thanks for response

S32_SCB_ICSR = 0x0440F890

S32_SCB_CFSR = 0x00000000

S32K146_FTM4.jpg

in archive Application FTM4 trouble my project

Thank you.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Oleg,

I don't know why yet, but it works when the vector table is moved to, for example:

pastedImage_2.png

BR, Daniel

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o_shantalosov
Contributor I

Hi Daniel,

I changed vector table location to 0x11000 and trouble goes away too.

What alignment should be VTOR?

 

Thank you.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Oleg,

Yes, it must be aligned.

Please take a look at ARMv7-M Architecture Reference Manual

https://developer.arm.com/docs/ddi0403/e/armv7-m-architecture-reference-manual 

B1.5.3 The vector table

pastedImage_2.png

BR, Daniel

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Oleg,

I don't see any issue in the description. 

Can you share the project?

What is the value of S32_SCB_ICSR and S32_SCB_CFSR?

BR, Daniel

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