Hello,
I would like to manage 2 PWMs (on pin PTC15 (FTM1_CH3, ALT2) & PTD8(FTM1_CH4, ALT6)), and just after starting counter, the signals (on pin) rise, but stay in high level (3,3v), so I have not PWM.
My source code comes from NXP example, but I show you it:
/* FTM1 Clocking */
PCC->PCCn[PCC_FTM1_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Ensure clk disabled for config */
PCC->PCCn[PCC_FTM1_INDEX] |= PCC_PCCn_PCS(2) /* Clock Src=1, 8 MHz SIRCDIV1_CLK */
| PCC_PCCn_CGC_MASK; /* Enable clock for FTM regs */
/* FTM1 Initialization */
FTM1->MODE |= FTM_MODE_WPDIS_MASK; /* Write protect to registers disabled (default) */
FTM1->SC = FTM_SC_PWMEN3_MASK /* Enable PWM channel 3 output */
|FTM_SC_PWMEN4_MASK /* Enable PWM channel 4 output */
|FTM_SC_PS(3); /* TOIE (Timer Overflow Interrupt Ena) = 0 (default) */
/* CPWMS (Center aligned PWM Select) = 0 (default, up count) */
/* CLKS (Clock source) = 0 (default, no clock; FTM disabled) */
/* PS (Prescaler factor) = 7. Prescaler = 128 */
FTM1->CONF |= FTM_CONF_BDMMODE(3); /* FTM functionnal mode debug */
FTM1->COMBINE = 0x00000000; /* FTM mode settings used: DECAPENx, MCOMBINEx, COMBINEx=0 */
FTM1->POL = 0x00000000; /* Polarity for all channels is active high (default) */
FTM1->MOD = 62500 -1 ; /* FTM1 counter final value (used for PWM mode) */
/* FTM1 Period = MOD-CNTIN+0x0001 ~= 62500 ctr clks */
/* 8MHz /128 = 62.5kHz -> ticks -> 1Hz */
/* FTM1, Channel 3 in PWM Mode */
FTM1->CONTROLS[3].CnSC = FTM_CnSC_MSB_MASK
|FTM_CnSC_ELSB_MASK; /* FTM1 ch3: edge-aligned PWM, low true pulses */
/* CHIE (Chan Interrupt Ena) = 0 (default) */
/* MSB:MSA (chan Mode Select)=0b10, Edge Align PWM */
/* ELSB:ELSA (chan Edge/Level Select)=0b10, low true */
/* FTM1, Channel 4 in PWM Mode */
FTM1->CONTROLS[4].CnSC = FTM_CnSC_MSB_MASK
|FTM_CnSC_ELSB_MASK; /* FTM1 ch4: edge-aligned PWM, low true pulses */
/* CHIE (Chan Interrupt Ena) = 0 (default) */
/* MSB:MSA (chan Mode Select)=0b10, Edge Align PWM */
/* ELSB:ELSA (chan Edge/Level Select)=0b10, low true */
FTM1->CONTROLS[3].CnV = 46875; /* FTM1 ch3 compare value (~75% duty cycle) */
FTM1->CONTROLS[4].CnV = 46875; /* FTM1 ch4 compare value (~75% duty cycle) */
/* Pins definitions
* ==============================
*
* Pin number | Function
* ----------------- |-----------
* PTC15 | FTM1CH3
* PTD8 | FTM1CH4 */
PCC->PCCn[PCC_PORTC_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTC */
PCC->PCCn[PCC_PORTD_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTD */
PORTC->PCR[15]|=PORT_PCR_MUX(2); /* Port C15: MUX = ALT2, FTM1CH3 */
PORTD->PCR[8]|=PORT_PCR_MUX(6); /* Port D8 : MUX = ALT6, FTM1CH4 */
/* Start FTM1 counter with clk source = external clock (SOSCDIV1_CLK)*/
FTM1->SC |= FTM_SC_CLKS(3);
Thanks by advance
Sebastien
