S32K144W LPO128K clock speed does not match data sheet

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S32K144W LPO128K clock speed does not match data sheet

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jparker
Contributor I

Hello, 

I am attempting to use the LPO clock as the clock source for the watchdog. During development, it became clear that the clock was not running at the expected frequency, as the watchdog would reset prior to the expected time.

 

From the data sheet ( https://www.nxp.com/docs/en/data-sheet/S32K1xx.pdf ), I expect the LPO to run between 113 - 141 kHz:

jparker_0-1745423151642.png

To measure the exact speed of the LPO clock, I configured a pin as CLKOUT and selected the LPO128K clock, and attached an oscilloscope to the pin. I measured the frequency at ~105kHz:

jparker_1-1745423582002.png

jparker_2-1745423591157.png

 

I have not made any modification to the LPOTRIM register in the PMC peripheral. When I inspected it with the debugger, I saw a value of 0b00010.

 

Some questions about this observed behavior:

- Is this the expected behavior, i.e. the clock frequency range on the data sheet is not correct? Am I looking at an outdated data sheet?

- Is this incorrect behavior, due to some error when the LPOTRIM value was written? Is there an errata regarding which parts are effected?

- The LPOTRIM register gives the ability to modify the output frequency of the LPO. Is it expected that the user somehow calibration the LPO during every power up? If so, what is the suggested process to accomplish that?

 

Thank you for you assistance.

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VaneB
NXP TechSupport
NXP TechSupport

Hi @jparker 

The Low Power Oscillator (LPO) frequency is trimmed to be close to 128kHz during production at room temperature. Each trim step adjusts the frequency by approximately 3kHz, so it cannot be trimmed precisely to 128kHz. The LPO frequency is heavily dependent on operational conditions, and there is no official specification for its characteristics.

The PMC_LPOTRIM register holds the trim value, which is automatically loaded from flash memory IFR after any reset. Please ensure that your software does not clear this value to maintain the trimmed frequency.

Also, there are significant differences in LPO frequency from part to part due to process variations. This is why the default LPOTRIM value is not 0b00000.

You might want to check out other threads on this topic for more info, they could be helpful.

About the sliding factors of the LPO frequency

LPO Clock out of range

S32K146 LPO clock source select

 

BR, VaneB

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jparker
Contributor I

Hello @VaneB , thank you for your response. Your information is appreciated. Can you clarify a few further points below?

>The Low Power Oscillator (LPO) frequency is trimmed to be close to 128kHz during production at room temperature. Each trim step adjusts the frequency by approximately 3kHz, so it cannot be trimmed precisely to 128kHz.

This is understandable. I expect a wide variation in part to part LPO frequencies, because of the wide range given in the data sheet. 

However, I am running this test using a device sitting on my desk. This should be reasonably close to ambient conditions. A measured output of ~105kHz is many ~3kHz steps away from 128kHz. It seems that the default PMC_LPOTRIM value with my device at or close to room temperature should result in a value much closer to the target frequency of 128kHz, and certainly within the range stated on the data sheet.

>The LPO frequency is heavily dependent on operational conditions, and there is no official specification for its characteristics.

How can this be true? The data sheet states the operating range for the LPO frequency. Is the data sheet not an official specification?

I would also like to reference the NXP-S32K1xx Series Safety Manual, revision 5. I will not duplicate the exact content here as the document is not public. Please refer to assumption [SM_067], in section 5.6.9, specifically the final sentence. If this assumption is followed, and the LPO clock does not have a specification for its characteristics, how is it possible to define the watchdog window values? 

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VaneB
NXP TechSupport
NXP TechSupport

Hi @jparker 

Unfortunately, we do not have a detailed correlation between temperature and LPO frequency. Generally, we only share the minimum (113KHz) and maximum (139KHz) values, which include aging and temperature aspects, as our SoC implementation supports LPO trimming.

To ensure greater accuracy of the LPO, you might consider using the LPOTRIM register in the PMC module. Additionally, here are some key considerations for measuring and ensuring the accuracy of the LPO:

  1. Use an oscilloscope or frequency counter to measure the LPO frequency directly. 
  2. Be aware that temperature variations can affect the LPO frequency. Ensure measurements are taken in a controlled environment or account for temperature changes.
  3. The LPO frequency may drift over time due to aging. Regular calibration or trimming may be necessary.
  4. Ensure that no other components or signals interfere with the LPO output during measurement.
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jparker
Contributor I

@VaneB 

>Generally, we only share the minimum (113KHz) and maximum (139KHz) values, which include aging and temperature aspects

 

This statement is what I expect, that the LPO clock frequency should be within the minimum and maximum values stated on the data sheet (though I need to note the maximum value you shared is for the S32K144, while the SoC that I am having trouble with is the S32K144W variant). However, it is not the case. The LPO clock is running below the minimum value, at ~105kHz. 

I understand that it is possible to modify the clock frequency using the PMC_LPOTRIM register, but I did not think that it was required to achieve the performance stated on the data sheet.

Can you please share the appropriate steps/process to calibrate the LPO to meet the stated data sheet performance?

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VaneB
NXP TechSupport
NXP TechSupport

Hi @jparker 

I have sent you a private message.

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