Hello all,
We have an application in which the micro is awakened from deep sleep (VLPS) by a falling edge interrupt in UART RX pin.
The problem is that apparently the first bit is lost, so we get a corrupted reception.
The baudrate is set to 115200. We think that lowering down the baudrate to 57600 should fix/improve the problem. But unfortunately this is not an option right now.
We have observed so far:
- When we disable deep sleep, the transition from VLPR run mode to RUN works just fine. From this, we are assuming that this transition takes less time and this is why the LPUART is able to sample the first bit correctly
- So, we decided to change the clock source of LPUART from SOSCDIV2 to SIRCDIV2. Our understanding is that SIRCDIV2 is also available in VLPS (I've checked that this clock is enabled for low power mode). Our expectation here was that the transition time from VLPS to RUN was not important anymore, because we expected the LPUART to keep working while in VLPS. So the reception should be just fine independenlty of in which mode the MCU is (VLPS or RUN)
However, it is still not working. Apparently, having the SIRCDIV2 as the clock source for LPUART does not solve our problem.
So, our question at this point would be if the LPUART can work in VLPS, so if our assumption is right that having the SIRCDIV2 as the clock source should make this work.
And more importantly, if anybody can help to have this working. Which is: the micro in VLPS awakened by LPUART reception, without loosing the first byte. Currently, the micro is awakened by falling edge interruption in LPUART RX line. I know that maybe also the LPUART RX interrupt should work as the wakeup source. But we currently have the falling edge in the RX pin.
Thanks a lot in advance.
Ricardo