S32K144 PROMBLE

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S32K144 PROMBLE

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shenlanzeng
Contributor I

problem of S32K144 LPSPI

I used  GPIO PTB14,PTB15,PTB16,PTB17 as LPSPI1‘s Pin,SPI send is ok(the signa PCS is i simulate),

the send waveform like that

pastedImage_3.png

but after received six bytes,it rest on

while((LPSPI1->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);

pastedImage_4.png

I found is the pastedImage_1.pngis disabled,but when i enable CONT and CONTC,the send is abnormality,if i want to use continuous model ,how can i config those registers。thanks for your help!

void Port_Init(void)
{
PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK; /*Enable clock for PORTB*/
PCC->PCCn[PCC_PORTA_INDEX] |= PCC_PCCn_CGC_MASK; /*Enable clock for PORTA*/
PORTB->PCR[14] |= PORT_PCR_MUX(3); /*PORT B14 :MUX = ALT3,LPSPI_SCK*/
PORTB->PCR[15] |= PORT_PCR_MUX(3); /*PORT B15 :MUX = ALT3,LPSPI_SIN*/
PORTB->PCR[16] |= PORT_PCR_MUX(3); /*PORT B16 :MUX = ALT3,LPSPI_SOUT*/
PORTB->PCR[17] |= PORT_PCR_MUX(3); /*PORT B17 :MUX = ALT3,LPSPI_PCS3*/
PORTA->PCR[6] |= PORT_PCR_MUX(3); /*PORT A6 :MUX = ALT3,LPSPI_PCS1*/
}

void LPSPI1_init_master(void)
{
PCC->PCCn[PCC_LPSPI1_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI1_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
LPSPI1->CR = 0x00000000; /* Disable module for configuration */
LPSPI1->IER = 0x00000000; /* Interrupts not used */
LPSPI1->DER = 0x00000000; /* DMA not used */
LPSPI1->CFGR0 = 0x00000000; /* Defaults: */
LPSPI1->CFGR1 = 0x00000009; /* Configurations: master mode*/ //1
LPSPI1->TCR = 0x2b000007; /* Transmit cmd: PCS3, 16bits, prescale func'l clk by 4. */
LPSPI1->CCR = 0x04090808; /* Clk dividers based on prescaled func'l clk of 100 nsec */
LPSPI1->FCR = 0x00000003; /* RXWATER=0: Rx flags set when Rx FIFO >0 *///3
LPSPI1->CR = 0x00000009; /* Enable module for operation */
}

void LPSPI1_Transmit_8bits (uint8_t *send,uint8_t len)
{
uint8_t i;
CS_LOW; //cs low
for(i = 0;i<len;i++)
{
while((LPSPI1->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0); // =0£» Transmit data not request
/* Wait for Tx FIFO available */
LPSPI1->TDR = send[i]; /* Transmit data */
LPSPI1->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
count = LPSPI1->FSR; /*FSR returns the number of words currently stored in the transmit FIFO*/
}
Delay1ms(2); //delay
CS_HIGH; //cs high
}

uint8_t rece_count = 0;

void LPSPI1_Receive_8bits (uint8_t *receive,uint8_t len)
{
uint8_t i;

for(i = 0;i<len;i++)
{
uint16_t j;
rece_count = LPSPI1->SR; //bit0:1:TDF,Transmit data is request bit1:0:Receive Data is not ready
//while(((LPSPI1->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0) && j<5000)j++;
while((LPSPI1->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0); // = 0 Receive Data is not ready
receive[i] = LPSPI1->RDR;
LPSPI1->SR |= LPSPI_SR_RDF_MASK;
// rece_count = (LPSPI1->SR & LPSPI_SR_REF_MASK)>>LPSPI_SR_REF_SHIFT;//LPSPI1->RSR;
//rece_count = LPSPI1->FSR;
}
}

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3 Replies

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

During a continuous transfer, if the transmit FIFO is empty, then the receive data is only written to the receive FIFO after the transmit FIFO is written or after the Transmit Command Register (TCR) is written to end the frame. (Section 49.4.2.2, RM rev.7).

You can end the continuous transfer with a new command where CONT = 0.

Regards,

Daniel

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金广陈
Contributor II

spi 非中断 和DMA   连续方式你解决了吗

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935348277
Contributor I

您好!我也遇到收的时候一直停在WHILE的循环里面,有没有什么办法解决的

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