void clock_pll_init(void)
{
//select SOSC as input clock to the Micro controller
SCG->SOSCCFG |= (1 << 2);// need to check this bit
//select the pll source as SOSC
SCG->SPLLCFG |= (1 << 0);
//set PREDIV to zero no need to devide the pll input clk
SCG->SPLLCFG |= (0 << 8);
//multiply the input 8 Mhz by 45 to make clock as 360 Mhz
SCG->SPLLCFG |= (29 << 16);
//bydefault the PLL output clock is devided by 2
//select SPLL_CLK as system clock in run mode
SCG->RCCR |= (6 << 24);
//set the division factor for core clock and system clock core_clk = pllclock/1 = 180Mhz /1 - 180 Mhz
SCG->RCCR |= (0 << 16);
//bus_clk = core_clk / 2 = 180 Mhz / 2 = 90 Mhz
SCG->RCCR |= (1 << 4);
//flash_clk = core_clk / 6 = 180Mhz / 6 = 30Mhz
SCG->RCCR |= (5 << 0);
//SPLLDIV1_CLK = PLL_CLK / 2 = 180Mhz / 2 = 90Mhz
SCG->SPLLDIV |= (2 << 0);
//SPLLDIV2_CLK = PLL_CLK / 4 = 180Mhz / 4 = 45Mhz
SCG->SPLLDIV |= (3 << 8);
//note:SPLLDIV1_CLK,SPLLDIV2_CLK these two clk can be used for any peripheral
}
void gpioInit(void)
{
//enable clock for PORTD
PCC->PCCn[PCC_PORTD_INDEX] |= (1 << 30);
//select the PD0 as output pin
PTD->PDDR |= (1 << 0);
//select PD0 as GPIO from mux
PORTD->PCR[0] |= (1 << 8);
}
void pitChannelInit(void)
{
//select SPLLDIV2_CLK for LPIT peripheral
PCC->PCCn[PCC_LPIT_INDEX] |= (6 << 24);
//enable clock for LPIT
PCC->PCCn[PCC_LPIT_INDEX] |= (1 << 30);
//enable clock for LPIT0 module
LPIT0->MCR = 1;
//enable channel0 interrupt
LPIT0->MIER = 1;
//load time period value to the timer value register
LPIT0->TMR[0].TVAL = 45000000;
//enable the timer channel 0
LPIT0->TMR[0].TCTRL |= (1 << 0);
}
when I am executing LPIT0->TMR[0].TVAL = 45000000; it is showing "Break at address "0xdeadbeee" with no debug information available, or outside of program code."
Can anyone tell me why I can not able to execute this line and what is the meaning of that note.
