S32K144: If 'Cache Enable' have an effect on 'driver Interrupt'

cancel
Showing results for 
Search instead for 
Did you mean: 

S32K144: If 'Cache Enable' have an effect on 'driver Interrupt'

457 Views
langweihua1643
Contributor I

Hello ,

In my project,I found that:

when I operate 'erase flash' or 'write flash' , syetem will reset,

therefore,I add sentence in main() as below(founded in cookbook) and system working normally:

LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1) | LMEM_PCCCR_ENCACHE(1);

 

but this sentence maybe have an effect on driver - interrupt(such as SPI,UART,etc.)

for example:

Before: I set UART(460800,int-priority-5)/SPI0(10M,int-priority-5)/SPI1(10M,int-priority-5) and system working normally

After:I have to set UART(460800,int-priority-5)/SPI0(1M,int-priority-7) SPI0(1M,int-priority-7)

If I don't set like After , interrupt maybe working weirdly(eg. data missing sometimes) ,I have to modify priority and cut down SPI-bautrate to guarantee data-completeness,

Dose anyone know this? 

If anyone has any idea,please share with me ,thanks very very much.

Labels (1)
0 Kudos
1 Reply

355 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello langweihua1643@163.com,

Regarding the reset, you probably launch the PFlash FTFC commands from the PFlash partition (there is only one PFlash partition on S32K144).

pastedImage_2.png
You need to execute the code that launches the FTFC commands (clear CCIF, wait until CCIF = 1) from a different flash partition (DFlash on S32K144) or SRAM.

Do you invalidate the Cache after the FTTC programming/erasing?

Regards,
Daniel

0 Kudos