S32K144 FlexCAN SUPV

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S32K144 FlexCAN SUPV

721 Views
Junkie
Contributor I

Hi, I met a problem when i access S32K144 FlexCAN_IMASK1 in user mode with CAN_MCR_SUPV=0 will cause BusFault, But the description of SUPV in RM is "0b - FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses.", I wonder it is normal ?

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Junkie,

The MCR[SUPV]=1 by default(FlexCAN is in Supervisor mode). Did you change the bit in Freeze mode? 

MCR[SUPV].png

I try to debug the can_pal_s32k144 example in S32 SDK for S32K1xx RTM 4.0.2.

First breakpoint: access the IMASK1 when MCR[SUPV]=1 did not cause BusFault.

flexcan_hw_access.c [line 505].png

Second breakpoint: access the IMASK1 when MCR[SUPV]=0 did not cause BusFault.

flexcan_hw_access.c [line 1272].png


Best Regards,
Robin
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Junkie
Contributor I

Do you enter user mode when SUPV = 0 ? I try your method, if in Supervisor mode (control[bit0] = 0), The phenomenon is as what you say , but when control[bit0] = 1 in user mode, BusFault will happen.

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Robin_Shen
NXP TechSupport
NXP TechSupport

Sorry for my previous reply. The core was in Supervisor (privileged) mode, I forgot change it in User(Unprivileged) mode.

Also cause BusFault when I access S32K144 FlexCAN_IMASK1 in User(Unprivileged) mode with CAN_MCR_SUPV=0. It seems that it does not match Table 55-19. Access permissions of S32K-RM Rev14

Table 55-19. Access permissions.png

I need to consult it with our AE team and will update as soon as I have their feedback. 

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Junkie
Contributor I

Ok, thank you,I will wait for that.

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Robin_Shen
NXP TechSupport
NXP TechSupport

Thanks for sharing your solution to me:
I have solved the problem, user mode access FlexCAN register is prevented by AIPS, as AIPS->OPACRL[0]_TP5 = 1, access FlexCAN register only in supervisor mode.

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