S32K144 + FS2303 SBC reset not released

[ThijsK]

Hi,

I have an issue with the reset line repetitivly being asserted between a S32K144 MCU and a FS2303 SBC.

In my design RSTB of the SBC is connected to PTA5 of the MCU with the recommended RC pull-up from the SBC datasheet:

(VDDIO = SBC V1 = 5V)

When reset reaches 3V, it gets pulled low to 0V and released after 120µs, in a repeating pattern:

Supply voltages all seem happy: 5V, 3.3V, 1.6V on SBC and 5V on the MCU.

Am I overlooking something, or what could be going on here?

Kind regards,

Thijs

#FS32K144ULT0VLHT #MFS2303BMBA3EP

[Robin_Shen]

Hi Thijs,

If it is a blank chip that has not been programmed, please download the program after unsecure MCU by mass erase.

Best Regards,
Robin
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[ThijsK]

You mean the MCU? The J-Link cannot connect because reset is not released (kept low). The SBC should be pre-configured by NXP:

[Robin_Shen]

I mass erased S32K144EVB-Q100, and the reset pin signal is exactly the same as yours.
But when I use the connect command of J-Link Command or Target->Connect of J-Flash, the reset pin will no longer reset periodically, and the program can be downloaded.

[ThijsK]

When I desolder the SBC and power the MCU directly with 5V, I do get the expected behavior you're also getting on the EVB:

So there is some interplay with the SBC, but what...

[Robin_Shen]

I only support S32K and I am not familiar with FS23 products. 
But according to my experience, if FS23 does not enter debug mode, then you need to feed the watchdog. Since your S32K1 has not downloaded the program and cannot feed the watchdog, FS23 will generate a reset signal to reset the S32K1.
The circuit on the S32K3+FS23 board is designed to allow FS23 to enter debug mode (normal power supply but no need to feed the watchdog).
If it is in the design evaluation stage (the S32K1 program does not yet include FS23 configuration and feeding the watchdog), it is recommended to refer to the S32K3 board to design the debug mode circuit.

Note: This power-up procedure manages that FS23 SBC starts with a disabled watchdog:

https://www.nxp.com/document/guide/getting-started-with-the-s32k31xevb-q100-evaluation-board-for-gen...

Here is the schematic: S32K31XEVB-Q100 Evaluation Design Files 

Please follow Figure 15. Debug mode.png to let the FS23 enter debug mode.

[ThijsK]

When I "unlock Kinetis" in J-Link commander RESET is released for ±200ms:

When I "connect" in J-Link (S32K144, SWD, 4000kHz), J-Link seems happy:

J-Link>connect
Device "S32K144" selected.


Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 11us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
InitTarget() end - Took 162ms
Found SW-DP with ID 0x2BA01477
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
[0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[0][1]: E0001000 CID B105E00D PID 003BB002 DWT
[0][2]: E0002000 CID B105E00D PID 002BB003 FPB
[0][3]: E0000000 CID B105E00D PID 003BB001 ITM
[0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU
Memory zones:
Zone: "Default" Description: Default access mode
Cortex-M4 identified.

However, RESET is only released for 750ms