S32K144 FLEXSPI/LPSPI CS pin

[antoine_monmarc]

Hello,

I'm using spi_pal demo from SDK S32DS_ARM_v2018.R1.

The master is configured to use FLEXIO SPI.

I have a question related to the CS pin. As you can see on the picture below, the CS is disabled between every bytes.

Is there a way to enable the CS pin as long as the master has data to transmit?

I looked into the FLEX SPI driver but I'm not familliar with it.

From Master side (running on another S32k148EVB board), it seems that the LPSPI IRQ is not triggered when the CS is enabled/disabled. I tryed to confirgure the interrupt on PTB0 using INT_SYS_EnableIRQ and INT_SYS_InstallHandler but it seems that it's never triggered.

Aslo the lpspi Callback is not triggered when the CS pin status change.

[antoine_monmarc]

Hello,

Yes by changing the master from Flexio to LPSPI we were able to use the continuous mode.

thank you.

[razva_tilimpea · Accepted solution]

Hi,

This feature is not available in Flexio, but you can use it on LPSPI. Please switch to LPSPI and select continuous mode.

In this mode CS is assert for all frames which are configured in your sending function.

I don't get exactly what are you trying to do with with the next SPI. Why both of them are masters? 

If PTB0 is routed to Flexio you can't use it as GPIO.

Best regards,

Razvan

[nxf47370]

Hi, Razvan-nicolae,

I noticed the S32K1xx RM Chapter 52.5.3" For CPHA=1, the select can remain asserted for multiple transfers and the timer status flag can be used to indicate the end of the transfer."  Does it mean that it can enable the CS pin as long as the master has data to transmit? If not, what does it mean?

Thanks, BR,

Han