S32K144: Cache enable/disable question

[dsfire]

Hello, all

I use the following statement for cache enable.
Q1: The following statement is ok? Does this statement can enable both instructions cache and data cache? And don't need other configuration for cache enable?
LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1) | LMEM_PCCCR_ENCACHE(1);

when i want to disable PFLASH cache temporarily before modifying PFLASH,
Q2: The following statement is ok? And don't need to flush data(in cache) to destination before PFLASH cache disable? If needed, how to flush?
MSCM->OCMDR[0u] |= MSCM_OCMDR_OCM1(0x3u);

when i want to disable cache temporarily,
Q3: The following statement is ok? And don't need to flush data(in cache) to destination before cache disable? If needed, how to flush?
LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1);

Regards,
Liu

[victorjimenez]

Hello Liu,

Regarding your questions please see my comments below.

Q1: The following statement is ok? Can this statement enable both instructions cache and data cache? And don't need other configuration for cache enable?

Your statement's correct, you only need that to enable the cache. 

Q2: The following statement is ok? And don't need to flush data(in cache) to a destination before PFLASH cache disable? If needed, how to flush?

This statement is correct. Noticed that when you do this the buffer is cleared automatically.

Q3: The following statement is ok? And don't need to flush data(in cache) to a destination before cache disable? If needed, how to flush?

Your statement is correct. However, I recommend you to add the following statements.

/* Enables the processor code bus to invalidate all lines in both ways.
and Initiate the processor code bus code cache command. */
base->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;

/* Wait until the cache command completes. */
while (base->PCCCR & LMEM_PCCCR_GO_MASK)
{
}

/* As a precaution clear the bits to avoid inadvertently re-running this command. */
base->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);‍‍‍‍‍‍‍‍‍‍‍

Have a great day,
TIC

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[dsfire]

Hello Victor,

Thanks for your reply.

Regarding your answer marked with red on Q2, what is the mean of "buffer is cleared"?

It will execute 2 steps: 1. flush cache content to destination; 2. invalidate cache content

Is it right?

I am concerned about the valid content behavior in cache.

Regards,

Liu

[victorjimenez · Accepted solution]

Hello Liu,

Sorry for the misunderstood. I was confused by questions two and three, please see my comments below.

when i want to disable PFLASH cache temporarily before modifying PFLASH,
Q2: The following statement is ok? And don't need to flush data(in cache) to destination before PFLASH cache disable? If needed, how to flush?
MSCM->OCMDR[0u] |= MSCM_OCMDR_OCM1(0x3u);

What you are deactivating here is the speculation buffer. When you deactivate this buffer it will be cleared automatically. You don't need to back up this information since it's already in the flash memory. However, since this is a read-only buffer, you don't need to deactivate it before modifying PFLASH.

when I want to disable cache temporarily,
Q3: The following statement is ok? And don't need to flush data(in cache) to destination before cache disable? If needed, how to flush?
LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1);

As mentioned before, your statement is correct, but I recommend you to add the lines that I mentioned in my last reply.

Here you don't need to back-up the data. By default, the local memory controller is in write-through mode. A write-through write hit updates the cache hit data and writes to the output bus.

Regards,

Victor.

[jochengerster]

Hello Victor

In Q2 you replied : ...you don't need to deactivate it before modifying PFLASH. 

But what about this scenario/problem described here?

https://community.nxp.com/message/880253?commentID=880253#comment-880253 

thanks

best regards

Jochen

[dsfire]

Hello Victor,

Thanks for your information.

It's cleared to me for Q2.

For Q3.

Just as you said, the default setting about region is Write-through, and there is no need to back-up the data.

So, if i change the setting to Write-back mode, do i need to bake-up the data if i use your statements as you mentioned before?

If yes, How i bake-up the data under Write-back mode.

Thanks again!!!

Regards,

Liu.

[victorjimenez]

Hello Liu,

In write-back mode initially, writing is done only to the cache. The write to the backing store is postponed until the modified content is about to be replaced by another cache block. Unfortunately, there isn't a way to control this. If you want to eliminate the risk of data loss you must use write-through mode.

Regards,

Victor.

[dsfire]

Hello Victor,

Thanks for your reply.

It's a great pity that there is no way to flush cache data to backing store in write-back mode.

Because i think the performance in write-back mode is better than in write-through mode.

But it's clear to me for these modes, thanks again.

Have a nice day!

Regards,

Liu.