void _hwio_can_init(void)
{
uint32_t i=0;
PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */
CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
CAN0->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKsrc=0: Clock Source = oscillator (8 MHz) */
CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/
CAN0->MCR |= CAN_MCR_FRZ_MASK+CAN_MCR_HALT_MASK; /*Sets FRZ, HALT*/
while (!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {}
/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */
CAN0->MCR = CAN0->MCR | 0x800;/*enable CANFD*/
CAN0->FDCTRL = CAN0->FDCTRL | 0x30000;/*data length 64MB*/
CAN0->CTRL1 = 0x00B30047; /* Configure for 500 KHz bit time */
/* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */
/* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */
/* so PRESDIV = 0 */
/* PSEG2 = Phase_Seg2 - 1 = 3 - 1 = 2 */
/* PSEG1 = 3 */
/* PROPSEG= Prop_Seg - 1 = 8 - 1 = 7 */
/* RJW: since Phase_Seg2 <4, RJW+1=3 so RJW=2. */
/* SMP = 1: use 3 bits per CAN sample */
/* CLKsrc=0 (unchanged): Fcanclk= Fosc= 8 MHz */
CAN0->FDCBT = 0x400; /* Configure for 2000 KHz bit time */
/* Time quanta freq = 4 time quanta x 2000 KHz bit time= 8MHz */
/* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */
/* so PRESDIV = 0 */
/* PSEG2 = 1 */
/* PSEG1 = 1 */
/* PROPSEG= 1 */
/* RJW=1. */
/* SMP = 1: use 3 bits per CAN sample */
/* CLKsrc=0 (unchanged): Fcanclk= Fosc= 8 MHz */
for(i=0UL; i<128UL; i++ ) { /* CAN0: clear 32 msg bufs x 4 words/msg buf = 128 words*/
CAN0->RAMn[i] = 0; /* Clear msg buf word */
}
CAN_RX_Init();
CAN_TX_Init();
CAN0_NVIC_init_IRQs();
CAN0->RXMGMASK = 0x1FFFFFFFUL; /* Global acceptance mask: check all ID bits */
CAN0->MCR = 0x0000081FUL + CAN_MCR_IRMQ_MASK; /* Negate FlexCAN 1 halt state for 32 MBs */
CAN0->IMASK1 = 0xFFFFF03FUL;//0xC3FFFF00;
while ((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {}
/* Good practice: wait for FRZACK to clear (not in freeze mode) */
while ((CAN0->MCR & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {}
/* Good practice: wait for NOTRDY to clear (module ready) */
_hal_SetIoChVal(_io_Mcanstb_o_chl_,0);
}
void CAN_RX_Init(void)
{
unint8 i;
// for(i=_FIRST_MESSAGE1_REC;i<(_FIRST_MESSAGE1_REC+RxNormalMesBuf);i++)
for(i=2;i<3;i++)
{
CAN0->RAMn[ 18U*i + 0U] = 0xC40F0000UL;//0x04000000UL;
CAN0->RAMn[ 18U*i + 1U] = RxCanBufferInfo[i-_FIRST_MESSAGE1_REC].id <<18UL;
CAN0->RXIMR[i] = RxCanBufferInfo[i-_FIRST_MESSAGE1_REC].MASK;
}
// //4**
// CAN0->RAMn[ 4U*30U + 0U] = 0xC4000000UL;//0x04000000UL;/* Msg Buf 4, word 0: Enable for reception */
// CAN0->RAMn[ 4U*30U + 1U] = 0x400UL<<18UL;//CanIdTab[_can_0x400].id;/* Msg Buf 4, word 1: Standard ID = CanIdTab */
// CAN0->RXIMR[30] = 0X1C000000UL;
//
// //7**
// CAN0->RAMn[ 4U*31U + 0U] = 0xC4000000UL;//0x04000000UL;/* Msg Buf 4, word 0: Enable for reception */
// CAN0->RAMn[ 4U*31U + 1U] = 0x700UL<<18UL;//CanIdTab[_can_0x701].id;/* Msg Buf 4, word 1: Standard ID = CanIdTab */
// CAN0->RXIMR[31] = 0x1C000000UL;
INT_SYS_EnableIRQ(CAN0_ORed_16_31_MB_IRQn);
INT_SYS_EnableIRQ(CAN0_ORed_0_15_MB_IRQn);
}
void CAN_TX_Init(void)
{
unint8 index;
CAN0->MCR = CAN0->MCR | 0x800;/*FD*/
// for(index = FIRST_CAN_ID; index < LAST_BUFTEC+1U; index++)
for(index = FIRST_CAN_ID; index < 1; index++)
{
CAN0->RAMn[ 18*index + 0] = 0xC80F0000UL;/* Msg Buf 18, word 0: Enable for reception */
/* EDL,BRS,ESI=0: CANFD not used */
/* CODE=4: MB set to RX inactive */
/* IDE=0: Standard ID */
/* SRR, RTR, TIME STAMP = 0: not applicable */
CAN0->RAMn[ 18*index + 1] = (CanIdTab[index].id<<18UL);/* Msg Buf 18, word 1: Standard ID = CanIdTab */
}
}
I put the CANFD code here
