Good day.
I have a problem with LPUART0 module. After initialization it start to recieve some data into FIFO even without conneced pins. LPUART1 works fine, settings for both modules are the same. Here's init code:
// Init. summary: 115200 baud, 1 stop bit, 8 bit format, no parity
void LPUART0_init(void)
{
PCC->PCCn[PCC_LPUART0_INDEX] &= ~PCC_PCCn_CGC_MASK; // Ensure clk disabled for config
PCC->PCCn[PCC_LPUART0_INDEX] |= PCC_PCCn_PCS(1) | PCC_PCCn_CGC_MASK;
LPUART0->BAUD = LPUART_BAUD_SBR(0x18) | LPUART_BAUD_OSR(16);
LPUART0->CTRL = LPUART_CTRL_RE(1) | LPUART_CTRL_TE(1) | LPUART_CTRL_RIE(1);
LPUART0->FIFO = LPUART_FIFO_TXFE(0) | LPUART_FIFO_RXFE(0) | LPUART_FIFO_RXFLUSH(1) | LPUART_FIFO_TXFLUSH(1);
}
registers:
LPUART0->STAT = 0x1E2C000
LPUART1->STAT = 0xC00000
LPUART0->FIFO = 0x800011
LPUART0->FIFO = 0xC00011
Maybe LPUART0 used for some other functions, that must be disabled before using this module?
Hi IvanTrashakhov,
Are you using S32K142EVB or custom board designed by yourself?
Need to pay attention to whether the LPUART0_RX pin voltage is the same as LPUART1_RX (whether the external circuit is the same).
There are two LPUART0_RX on S32K142EVB, among which PTB0 (LPUART0_RX) pin is connected to LIN_RX of TJA1027T/20.
It is recommended to try to modify the lpuart_echo_s32k142 example in the SDK, test whether it is normal after changing from LPUART1 to LPUART0 (remember to modify the corresponding pin)
Best Regards,
Robin
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I am using custom board.
Immediatly after initialization procedure LPUART0->STAT bit RAF becomes to '1' and stay in this state. This happens even when all pins are disconnected from module.
Would you please show the value of all LPUART registers during debug?
This is convenient to compare whether the register configuration is Except for assigning different pins, there is no obvious difference between LPUART0 and LPUART1.
Sorry to keep you waiting, I used your LPUART initialization function and cannot reproduce this problem.
Have you set the pin function, such as:
PCC->PCCn[PCC_PORTC_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTC */
PORTC->PCR[6]|=PORT_PCR_MUX(2); /* Port C6: MUX = ALT2, UART1 TX */
PORTC->PCR[7]|=PORT_PCR_MUX(2); /* Port C7: MUX = ALT2, UART1 RX */
PCC->PCCn[PCC_PORTA_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTA */
PORTA->PCR[3]|=PORT_PCR_MUX(6); /* Port A3: MUX = ALT6, UART0 TX */
PORTA->PCR[2]|=PORT_PCR_MUX(6); /* Port A2: MUX = ALT6, UART0 RX */