S32K118 writing data to EEE will interrupts PDB triggered ADC sample

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

S32K118 writing data to EEE will interrupts PDB triggered ADC sample

2,242 次查看
13761826501
Contributor III

Hi Dear,

Currently, I have encounter a problem that Writing data to Emulated EEPROM using PE generated code function "FLASH_DRV_EEEWrite(&flashSSDConfig, addr, size, pData);"  will stop the ADC sample process. ADC choose a Hardware trigger by PDB which has been configured to continuous mode that to trigger ADC sample background automatically.

I really don't know the reason to this problem, anyone could help me will be greatly appreciated!

I upload my project file, It's simple to know and test my code in directory {project}/Sources/Adc and {project}/Sources/Eeprom. I hope some can help me find why cyclically write to EEE will affect ADC sample?

IDE SEWDS.ARM.2.2

此视频当前正在处理中。请在几分钟后重试。
(在“我的视频”中查看)

Thanks a lot!

0 项奖励
回复
3 回复数

2,168 次查看
danielmartynek
NXP TechSupport
NXP TechSupport

Hi 13761826501@163.com,

I have just gone through the project briefly, it is quite complex.

Could you maybe describe why do you think that a write to EEPROM stops the PBD-ADC operation?

I have noticed that you disable interrupt before each EEPROM write.

Since this eeprom operation can take some time, the interrupts might be disabled for too long.

pastedImage_2.png

Regards,

Daniel

0 项奖励
回复

2,168 次查看
13761826501
Contributor III
Hi Daniel,
 Thank you very much for your prompt help!
After, I tried experiment: (before all below testing , the wathdog is under close state)
1. The interrupt operation in EEPROM wirte has been deleted
      status_t EEPROM_Write(uint32_t addr, const uint8_t * pData, uint32_t size)
      {
          DEV_ASSERT(flashSSDConfig.EEESize != 0u);
          DEV_ASSERT(addr < flashSSDConfig.EEESize);
          DEV_ASSERT((addr+size) < flashSSDConfig.EEESize);
          DEV_ASSERT(pData != NULL);
          status_t errorCode = STATUS_SUCCESS;
          uint8_t u8_try_cnt = 0U;
          addr = addr + flashSSDConfig.EERAMBase;
          do
          {
               ..omitted
            } while ((u8_try_cnt < 3U) && (errorCode != STATUS_SUCCESS)); /* Give 3 chances for writing all data that             pData pointed */
             /* u16 */
            return errorCode;
            }
2. Close All Application task
         void OS_Dispatcher(void)
         {
                UNS16 i,j;
                for(;;)
                {
                       OS_SetMonitorPollingCount(eMonitorPollingExecuteRoutine,0x00);
                        for (i = 0; i < OSRTNS_ExecuteRoutineParameterRtnSize; i++)
                       {
                            if (OSRTNS_ExecuteRoutineManageTable[i].m_ucExecuteRoutineEvent == 0x01)
                             {
                                   // OSRTNS_ExecuteRoutineParameterTable[i].m_pExecuteRoutine(); /* All appliation task commented */
                                     OSRTNS_ExecuteRoutineManageTable[i].m_ucExecuteRoutineEvent = 0x00;  
                              }     
           } 
             for(j=0; j<ScheduleTableSize; j++ )
             {
                  if( 0U != stOSTimerParameter.m_ucTimerEvent[j] )
                  {
                      stOSTimerParameter.m_ucTimerEvent[j] = 0x00U;
                      if( (UNS16)eTimerEvent1ms == j )
                      {
                          OS_SetMonitorPollingCount(eMonitorPollingScheduleRoutine,0x00);
                      }
                      scheduleTable[j](j);
                      if( NULL != ScheduleRoutine[j] )
                      {
                          ScheduleRoutineStatus[j] = (*(ScheduleRoutine[j]))(ScheduleRoutinePass[j]);
                      }
                  }
                 }
             }
            }
3. Put EEE_test() in a 200ms scheduler.
      static void Sch_eTimerEvent200ms(UNS16 index)
      {
             (void)(index); /*avoid warning */
             EEE_Test();   
         }
4. The data size write to EEE each time increament by *2.
 . The test results are commented in below code comments
        sourceBuffer[0u]++;
        sourceBuffer[1u]++;
        sourceBuffer[2u]++;
        sourceBuffer[3u]++;
        sourceBuffer[4u]++;
        sourceBuffer[5u]++;
        sourceBuffer[6u]++;
        sourceBuffer[7u]++;
        sourceBuffer[8u]++;
        sourceBuffer[9u]++;
        sourceBuffer[10u]++;
        sourceBuffer[11u]++;
        sourceBuffer[12u]++;
        sourceBuffer[13u]++;
        sourceBuffer[14u]++;
        sourceBuffer[15u]++;
        sourceBuffer[16u]++;
      // EEPROM_Write(4, sourceBuffer,1);  /* AD work normally */
      // EEPROM_Write(4, sourceBuffer,2);  /* AD work normally */
      //EEPROM_Write(4, sourceBuffer,4);  /* AD work normally */
     // EEPROM_Write(4, sourceBuffer,8);  /* AD work normally */
      EEPROM_Write(4, sourceBuffer,16);  /* Abnormal, the same phenomena shown in video */
    
      It seems that the more data write to EEE every cycle the more the risk to the ADC .
      I don't think 16 bytes *2000us will be affected when running in a 200ms scheduler.
      Further , I put the  EEE_Test() in one second scheduler. Bad thing happen, the same phenomenon "The ADC           blocked"
                  static void Sch_eTimerEvent1000ms(UNS16 index)
                   {
                          EEE_Test();
                }
 5. I'd rather put EEE_Test() before the OS_Dispather() in main() and change change EEE_Test() so as to write a brand new data to EEE after reset,
   unfortnately , ADC samples are also blocked when writing a 32 bytes date.
void EEE_Test(void)
{
 uint16_t i;
 uint32_t t;
 address = flashSSDConfig.EERAMBase;
    for (i = 0u; i < BUFFER_SIZE; i++)
    {
       // sourceBuffer[i] = i;
        t = *((uint32_t *)address);
        address = address+4;
    }
    /* Try to write data to EEPROM if FlexRAM is configured as EEPROM */
    if (flashSSDConfig.EEESize != 0u)
    {
        address = flashSSDConfig.EERAMBase;
        size = sizeof(CONF_EE);
       // ret = EEPROM_Write(0, sourceBuffer,BUFFER_SIZE);
       // DEV_ASSERT(STATUS_SUCCESS == ret);

        /* Try to update one byte in an EEPROM address which isn't aligned */
        address = flashSSDConfig.EERAMBase + 1u;
        size = sizeof(uint8_t);
        //sourceBuffer[0u] = 0xFFu;
        (sourceBuffer[0u]++);
        (sourceBuffer[0u]++);
        sourceBuffer[1u]++;
        sourceBuffer[1u]++;
        sourceBuffer[2u]++;
        sourceBuffer[2u]++;
        sourceBuffer[3u]++;
        sourceBuffer[3u]++;
        sourceBuffer[4u]++;
        sourceBuffer[4u]++;
        sourceBuffer[5u]++;
        sourceBuffer[5u]++;
        sourceBuffer[6u]++;
        sourceBuffer[6u]++;
        sourceBuffer[7u]++;
        sourceBuffer[7u]++;
        sourceBuffer[8u]++;
        sourceBuffer[8u]++;
        sourceBuffer[9u]++;
        sourceBuffer[9u]++;
        sourceBuffer[10u]++;
        sourceBuffer[10u]++;
        sourceBuffer[11u]++;
        sourceBuffer[11u]++;
        sourceBuffer[12u]++;
        sourceBuffer[12u]++;
        sourceBuffer[13u]++;
        sourceBuffer[13u]++;
        sourceBuffer[14u]++;
        sourceBuffer[14u]++;
        sourceBuffer[15u]++;
        sourceBuffer[15u]++;
        sourceBuffer[16u]++;
        sourceBuffer[16u]++;
       EEPROM_Write(4, sourceBuffer,32);
        //DEV_ASSERT(STATUS_SUCCESS == ret);
        /* Then verify */
        if (sourceBuffer[0u] != *((uint8_t *)address))
        {
            /* Failed to update data to EEPROM */
        }
        EEPROM_Read(0, readBuffer, BUFFER_SIZE);
    }
    else
    {
    }
}
6. It seemed that frequent write data  more than 16 bytes to EEE is prohibbited, And the  more  date that write to EEE will have more demage to  system such as block the ADC sampling. I think there might be a wrong configured items in the Process Expert project. Could you help me check them? and if I have more than 500 bytes data write to EEE in one second , are there some suggestions that you can provide me about how to design this writing-to-eeprom.?
Thank you so much!
0 项奖励
回复

2,168 次查看
danielmartynek
NXP TechSupport
NXP TechSupport

Hello 13761826501@163.com,

Sorry for the delay.
As I said, the project is very complex.
But I don’t see any reason why an EEPROM/FTFC operation would stop the PDB/ADC operations.
If I understand, you use DMA to transfer the ADC results to SRAM.
Do you see any PDB, DMA, FTFC errors when it appears to be halted?
It really requires some debugging.
You can actually route some ADC COCO, PBD triggers to TRGMUX_OUTx pins.

pastedImage_2.png


Anyway, if it is really halted, there must be some errors reported in the peripheral registers.

BR, Daniel

0 项奖励
回复