S32K118 Program Debug is ok，but can not run after power-on again

[a767427254]

hello NXP 

I have a question about S32K118 that when I debug my Program with S32DS , the program  runs well , but when I load it to fiash and power-on again ,the program can not be run, I do not know  how to solve it.

please help me thanks .

[rahulpkumar-2612]

I am facing the same issue. Is it resolved for you? Could you please tell me how to if it is resolved?

Thank you in advance.

[happybaby8882]

Do you resolve this problem and how? I got the same problem today.

[Robin_Shen]

Have you try to test examples in SDK? for example: the lpit_periodic_interrupt_s32k118 example

Please check the Optimization Level, will None(-O0) work?

Best Regards,
Robin

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[a767427254]

Connection from "127.0.0.1" via 127.0.0.1. Connection from port "35053" to 6224
Connection from "127.0.0.1" via 127.0.0.1. Connection from port "35061" to 7224
Telnet server running on 127.0.0.1:51794
Searching for FreeRTOS Kernel Symbols...
rsp_qC - qSymbol: 707843757272656E74544342
pxCurrentTCB not found. FreeRTOS analysis not enabled.
Copyright 2018 P&E Microcomputer Systems,Inc.
Command Line :E:\NXP\S32DS_ARM_v2.2\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_4.4.6.201912192052\win32\pegdbserver_console -device=NXP_S32K1xx_S32K118F256M4 -startserver -singlesession -serverport=7224 -gdbmiport=6224 -interface=USBMULTILINK -speed=5L
P&E Interface detected - Flash Version 6.15

CMD>RE

Initializing.
Target has been RESET and is active.
CMD>CM E:\NXP\S32DS_ARM_v2.2\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_4.4.6.201912192052\win32\gdi\P&E\supportFiles_ARM\NXP\S32K1xx\freescale_s32k118f256m4_pflash_dflash_eeprom.arp

Initializing.
Initialized.

;version 1.01, 12/03/2019, Copyright 2019 P&E Microcomputer Systems, Inc. All rights reserved. www.pemicro.com [s32k118f256m4_x_pflash_dflash_eeprom_m0]

;device freescale, s32k118f256m4, pflash_dflash_eeprom

;begin_cs device=$00000000, length=$14000800, ram=$1FFFFC00

Loading programming algorithm ...
Done.
Programming sequency is : erase, blank check, program, and verify {default}
CMD>VC
Verifying object file CRC-16 to device ranges ...
block 00000000-000000BF ...
Calculated CRC-16 does not match block. (File = $4DA7, Device = $ED3C)
Current content of flash does not match application to be programmed

CMD>EM

Erasing.
Module has been erased.
Reloading programming algorithm ...
done.
CMD>PM

Programming.
Processing Object File Data ...


.
Programmed.
CMD>VC
Verifying object file CRC-16 to device ranges ...
block 00000000-000000BF ...
Ok.
block 00000400-000072AB ...
Ok.
Checksum Verification Successful. (Cumulative CRC-16=$25A3)

CMD>RE

Initializing.
Target has been RESET and is active.

Starting reset script (E:\NXP\S32DS_ARM_v2.2\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_4.4.6.201912192052\win32\gdi\P&E\supportFiles_ARM\NXP\S32K1xx\S32K118F256M4.mac) ...
Filling .
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done

Reset script (E:\NXP\S32DS_ARM_v2.2\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_4.4.6.201912192052\win32\gdi\P&E\supportFiles_ARM\NXP\S32K1xx\S32K118F256M4.mac) completed.

Interrupt command received. Halting execution.

Starting reset script (E:\NXP\S32DS_ARM_v2.2\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_4.4.6.201912192052\win32\gdi\P&E\supportFiles_ARM\NXP\S32K1xx\S32K118F256M4.mac) ...
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done

Reset script (E:\NXP\S32DS_ARM_v2.2\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_4.4.6.201912192052\win32\gdi\P&E\supportFiles_ARM\NXP\S32K1xx\S32K118F256M4.mac) completed.

CPU reset by debugger.

No breakpoints currently set.

above is console printed data ,   below is link file seted data 

HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000200;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000200;

M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x00C0;

/* Specify the memory areas */
MEMORY
{
/* Flash */
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000000C0
m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0003FBF0

/* SRAM_L */
m_custom (RW) : ORIGIN = 0x1FFFFC00, LENGTH = 0x00000400
/* SRAM_U */
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x000030C0
m_data_2 (RW) : ORIGIN = 0x200030C0, LENGTH = 0x00002740
}