I don't know the specifics of this part. Speaking to EEPROM failure in general there is not hard cut off point.
If the datasheet says "100,000" writes it is not going to fail at 100,001.
Consider the EEPROM cell to be a capacitor, where the bit is stored.
Each write/erase (It is actually the erasing that does the damage, not the writes) slightly degrades the capacitor by increasing its leakage.
A fresh write will charge the capacitor, however because of the leakage it will blead off in time.
This means that reading back the data right after the write will read back the data that was written, so it will appear correct.
This leakage is temperature dependent and voltage dependent. The higher the temperature the faster the reads will be invalid. After the data sheet value at room temperature things may appear to work for millions of writes, while operating at 85'C it could only return the correct data for thousands of writes beyond the data sheet limit value.
The bottom line is it is up to you to some how manage the write endurance of a EEPROM sector.
The obvious, bad, solution is to have a counter in the EEPROM telling the write/erase for a given sector then move a pointer to use a new sector. Where this simple solution fails is the sector that the counter is in is what will wear our first.
Using things like Gray Encoding can help limit the endurance wear in some applications.
More info can be found here:
"High-Reliability and High-Frequency EEPROM Counter"
https://www.microchip.com/en-us/application-notes/an1449
More on the failure mechanism here:
https://ww1.microchip.com/downloads/en/AppNotes/01019A.pdf
https://ww1.microchip.com/downloads/en/AppNotes/00601.pdf
If someone knows of the ideal solution to EEPROM endurance I'd like to know myself...
