Thanks! With the below configuration i was able to read data of 4 adc channels with back to back conversion.
PCC->PCCn[PCC_PDB0_INDEX] |= PCC_PCCn_CGC_MASK; /* Enable bus clock in PDB0 */
PDB0->SC |= PDB_SC_TRGSEL(0xF) | /* b1111: Software trigger is selected */
PDB_SC_PRESCALER(1) | /* Prescaler: 010 = sysclck/(2*MULT) = 80 / (2*1) = 8MHz */
PDB_SC_MULT(0) | /* 00: Multiplication factor is 1. */
PDB_SC_PDBEN_MASK; /* 1: PDB enabled */
PDB0->CH.C1 |= PDB_C1_BB(0xe) | /* DLY : pre-trigger from PDB DLY */
/* DLY[3:1] : back-to-back enabled */
PDB_C1_TOS(0x00) | /* Pretrigger Output Select: 0=bypassed , 1=enabled */
PDB_C1_EN(0xf); /* PDB channel's [3:0] pre-trigger enabled */
PDB0->SC |= PDB_SC_LDOK_MASK;
But i was trying to configure 8 adc channels with PDB0, looking for your help with the configuration.
I could see in the RM that this micro supports up to 8 configurable PDB channels for ADC hardware trigger.
Thanks in advance!