S32K116 ERM EAR0 has an fixed offset

[Helloyt]

Hi,

    I tried to test the feedback of ERM when i read different area of SRAM with signal bit ECC error injected, but wen i test the address of SRAM_U  in S32K116 with SDK3.0.0 ,I found that it always has an fixed offset 0x3C(if the read SRAM_U address greater than 0x20003800 - 0x3C ,the EAR0 will always be 0x200037FC)

    p.s. optimization level is -O0

    followint are the debug pics: 

• pic1

• pic2

• pic3

address i tried to read:

#define MEM_TEST_ADDRESS1 (uint32_t *)0x20000000U
#define MEM_TEST_ADDRESS2 (uint32_t *)0x20003000U
#define MEM_TEST_ADDRESS3 (uint32_t *)0x200037E0U

in pic1 and pic2 , you can see than when i read 0x20000000 ,with EAR0 0x2000003C feedback

when i read 0x20003000 with EAR0 0x200000C0 feedback

and in pic3 ,when i tried to read 0x200037E0 with 0x200037FC feedback

• pic4

but,inexplicably,sometimes it could feedback the right address ,as you see in pic4,with no config changed 

I realized that if i set breakpoint before i read specific address and use signal step to debug,it will generate a 0x3c offset although all disassmbly access are right(i need to check disassembly code),but when i set breakpoint after the read access ,the offset seems will not generate anymore.

so what would response to the error?

[Robin_Shen]

Hi

I debug it with on board OpenSDA, set only one breakpoint before read specific address. It did not generate a 0x3c offset.

Best Regards,
Robin

[Helloyt · Accepted solution]

Hi,@Robin_Shen

Thanks for your answer, my IDE is S32DS 2018 wih SDK3.0.0 ,but I supposed that the main difference is that my debugger is Jlink.

the first time I try to debug step by step, it has an fixed offset but after a SW reset by debugger, the offset not occurred any more.

by the way, I found that if I debug step by step meanwhile read the data in memory , the offset also changed, So it seems the best solution for any debug device is to run without pause