S32K SAI request for DMA

[jakub_mielczare]

Hello,

Suppose that DMA is programmed to transfer 4 samples (4 bytes each) to SAI0 TX in one minor loop. There are two minor loops per major loop. SAI TX triggers the DMA transfer through request.

If watermark for SAI TX FIFO is set to 1 what will be the DMA transfer behavior:

opt. 1: SAI triggers request when FIFO level is less or equal 1, DMA performs 1 minor loop (transfers 4 samples), then DMA waits for next request from SAI (when FIFO level is again less or equal 1) to transfer the second minor loop

opt. 2: SAI triggers request when FIFO level is less or equal 1, DMA performs 1 minor loop (transfers 4 samples), then DMA peforms the second minor loop, not waiting for next request from SAI

Also a question: how does SAI<->DMA request handshaking work?

Thank you,

Jakub

[jorge_a_vazquez]

Hi Jakub Mielczarek

It would be the option 1, each FIFO request trigger a transfer of minor loop. I recommend you to check the following document:

https://www.nxp.com/docs/en/application-note/AN12202.pdf 

Hope this helps,
Have a great day,
TIC

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[jakub_mielczare]

Hello,

We suspect that in this configuration DMA is writing to the SAI FIFO more samples that can fit in it as we hear channel shifting. Are you sure that option 2 is not the case?

Thank you,

Jakub

[jorge_a_vazquez]

Hi Jakub

If you have set FIFO to 1 and you active DMA transfers, then as you have fewer data in your FIFO that you indicate with your watermark, DMA will transfer 1 sample, then, as you now have an equal number of data in your FIFO buffer (1 sample), then DMA will transfer another sample. There are two requests by the SAI FIFO watermark when one transfer finished, DMA starts the second because FIFO content is equal to watermark.

You can check the part "4.7.1. Triggering SAI transmission/reception operation" and the part "4.5. SAI FIFO and DMA/Interrupt generation" in the document https://www.nxp.com/docs/en/application-note/AN12202.pdf 

Hope this helps.

Regards

Jorge Alcala

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[jakub_mielczare]

Hi Jorge,

I think I was not clear about my configuration. DMA is programmed to transfer 4 (32bit wide) samples per each TX channel of SAI0 (4 channels in total) in one minor loop. Each TX channel is served by dedicated DMA channel. DMA channel serving SAI0_D0 is linked to one serving SAI0_D1 and so on for all SAI0 channels. DMA channel for SAI0_D3 is not linked back to SAI0_D0. Only the first DMA channel (for SAI0_D0) is triggered by SAI.

So I understand, that when FIFO level is 1 or less, 4 samples will be written to each SAI0_Dn. Then FIFO fill level should be greater than 1. Which would mean from you post, that the next minor loop will be triggered only, when FIFO level drops again to 1 or 0. But my suspicion is that it gets triggered sooner.

Can you confirm?

Regards,

Jakub

[jorge_a_vazquez]

Hi Jakub Mielczarek

So you have 4 DMA channels and each of them transmits 4 bytes, correct?

This should not change anything, the first DMA transfer will be trigger only by request of the "FIFO level drops" and the linked channel will trigger other DMA channels.

I would like to point out that if you have the SAI Transmitter enabled, then SAI will start transfer data as soon as the TDRx has any data, so it will drop the FIFO level and it will trigger another DMA transfer. This process will happen fast and you could think that DMA transfer is triggering sooner than it should trigger.

Regards

Jorge Alcala

[jakub_mielczare]

Hi Jorge,

Yes, I have 4 DMA channels, each transfers 4bytes x 4 per each minor loop, there are 2 minor loops in each major loop.

One correction to my description: the last DMA channel (for SAI_D3) is not linked back to DMA channel for SAI_D0.

DMA channel for SAI_D0 is triggered only by SAI0 DMA request.

Does this change your answer?

Regards,

Jakub

[jorge_a_vazquez]

Hi Jakub

Sorry but I don't see any difference between your Apr 23 post and your Apr 15 post. So, there is not difference, DMA minor loop transfer will be triggered by request of SAI FIFO buffer equal to 1 or 0. According to your description, the behavior that you are seeing is normal: The content of SAI FIFO buffer is 0, so a DMA transfer is triggered because your watermark is 1, then your content in SAI FIFO buffer is 1, and again DMA transfer is triggered because your watermark is equal to your FIFO content.

Could you clarify how are you checking that the DMA transfer doesn't wait for a SAI request?

Regards

[jakub_mielczare]

Hi Jorge,

I am sending sine wave of different frequency on each channel.

When I set watermark to 0 I am getting SAI underruns, but not channel switching. When I set watermark to 1, then once every few seconds I am getting a channel switch. That is why I suspect that DMA writes more data to SAI FIFO than can fit in it (some samples would be discarded by FIFO in such case and TDM would loose sync with the stream).

Regards,

Jakub

[jorge_a_vazquez]

Hi Jakub

Could you share the project or parts of the code that you are suing? I would highly recommend using a watermark bigger than 1. For example, you could try using 4, please note that you have to fill up the FIFO buffer before enabling it, so you can have proper DMA triggers when FIFO is 4 and your FIFO should never be empty.

Best regards

Jorge Alcala

[jakub_mielczare]

Hi Jorge,

Attached is part of my project's code. The function "stream_start()" calls set up of the DMA and then function "audio_enable()" starts SAI.

In the folder EVB_32A there are configuration files with constants used by the project.

When "TX_WATERMARK_0" is set to 0 I am getting SAI underruns. When I change it to 1 I am getting channel shifting.

Let me know if you need more clarification.

I also have one more question: if major/minor loop DMA interrupts are used, does DMA wait for CPU to service the interrupt before starting next transfer?

Best regards,

Jakub

[jorge_a_vazquez]

Hi Jakub

Unfortunately, there are some parts missing, so I cannot test the code in my side. I was checking the code and I don't see any incorrect implementation, but I noticed that you are using the Enet module also. Are you able to isolate the SAI code, so we can discard that there is a problem related to other modules?

Regarding your other question: No, CPU and DMA state machine work independently, so if you use interrupts, the CPU is serving the handler and there is another DMA request, the DMA request should be attended normally.

Regards

Jorge Alcala