S32 cannot comunicate with sbc uja 1167 over LSPI0

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

S32 cannot comunicate with sbc uja 1167 over LSPI0

Jump to solution
997 Views
chris21
Contributor II

Hi,

 

I have a S32k144 solderd as a 48 pin contorller on my pcb. I tried different ways I can not see the SCK on ptb2. All communication to the connected sbc failed. Is there a specific way to activate SPI communication?

0 Kudos
1 Solution
936 Views
chris21
Contributor II

It seems to work now.

I took all file and made up a new project with them

While making a diff and studiing the files for in project, I found out that eclipse was using files from my origan .zip file.

I used this .zip file at import. This behavoir is very strange behavoir for me.

This was coded in startup.d:

//<myname>/profdaten/<myname>/Eigene\ Dateien/SBC_1169.ZIP_expanded/SBC_1167/include/startup.h \
//<myname>/profdaten/<myname>/Eigene\ Dateien/SBC_1169.ZIP_expanded/SBC_1167/include/device_registers.h \

...and it should look like this

C:/..<myname>../workspaceS32DS.3.4/TESTING1/include/startup.h \
C:/..<mynamw>../workspaceS32DS.3.4/TESTING1/include/device_registers.h \

Nevermind. This fault costs me 2 days. If I would have a better understanding using eclipse, I

like eclipse a bit more. From my point of view a simple.bat file in combination with Notepad++, will do also.

 

View solution in original post

0 Kudos
6 Replies
983 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@chris21

       Is your SPI module configured correctly?
       Because even if UJA1167 is not connected, if you configure the module correctly, the SCK pin should have a waveform.
       So I think the first step should be to test whether your SPI module configuration is correct. There is an example of S32K144 SPI module configuration in S32 DS. You can refer to this example to troubleshoot the software first. If possible, it is recommended to remove the SBC first.

         There is driver support for UJA1169 in S32 DS. You can search for S32K144EVB related information on the official website. This design uses S32K144 + UJA1169, which may be helpful to your design.

etc.S32K144 LSP0 & LSP1 

Senlent_0-1628565191818.png

S32K144 + UJA1169

Senlent_1-1628565426423.png

BR

Jim.

0 Kudos
975 Views
chris21
Contributor II

This is what I did:

Project test on EVB using LPSPI1 from cookbook– working

Project test on EVB using LPSPI0 adjusted code – working

 

Project test on PCB with adjusted code – not working

  • Clock always high, no data

Project to toggle Clock Port in I/O configuration on PCB – working

Set up LPSPI1 for 48Pin S32K144 using PTD1-3 – not working

  • Clock always high, no data

I use Pemicro for programming and debugging.

This my code:

/*

 * main implementation: use this 'C' sample to create your own application

 *

 */

#include "S32K144.h"

#include "LPSPI.h"

#include "clocks_and_modes.h"

 

 

uint16_t tx_16bits = 0xFD00;  /* SBC UJA1169: read Dev ID Reg @ 0x7E (expect non-zero)*/

                                /* Note: Obsolete EVB with MC33903 example used 0c2580 */

                                /*       to read SAFE reg flags (expect nonzero result).*/

uint16_t LPSPI0_16bits_read;  /* Returned data in to SPI */

 

 

#if defined (__ghs__)

    #define __INTERRUPT_SVC  __interrupt

    #define __NO_RETURN _Pragma("ghs nowarning 111")

#elif defined (__ICCARM__)

    #define __INTERRUPT_SVC  __svc

    #define __NO_RETURN _Pragma("diag_suppress=Pe111")

#elif defined (__GNUC__)

    #define __INTERRUPT_SVC  __attribute__ ((interrupt ("SVC")))

    #define __NO_RETURN

#else

    #define __INTERRUPT_SVC

    #define __NO_RETURN

#endif

 

 

void WDOG_disable (void){

  WDOG->CNT=0xD928C520;     /*Unlock watchdog*/

  WDOG->TOVAL=0x0000FFFF;   /*Maximum timeout value*/

  WDOG->CS = 0x00002100;    /*Disable watchdog*/

}

 

void PORT_init (void) {

  PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */

  PCC->PCCn[PCC_PORTD_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */

 

//  PORTD->PCR[0]|=PORT_PCR_MUX(3); /* Port B14: MUX = ALT3, LPSPI0_SCK */

//  PORTD->PCR[1]|=PORT_PCR_MUX(3); /* Port B15: MUX = ALT3, LPSPI0_SIN */

//  PORTD->PCR[2]|=PORT_PCR_MUX(3); /* Port B16: MUX = ALT3, LPSPI0_SOUT */

//  PORTD->PCR[3]|=PORT_PCR_MUX(4); /* Port B17: MUX = ALT3, LPSPI0_PCS3 */

 

 

  PORTB->PCR[2]|=PORT_PCR_MUX(3); /* Port B14: MUX = ALT3, LPSPI0_SCK */

  PORTB->PCR[3]|=PORT_PCR_MUX(3); /* Port B15: MUX = ALT3, LPSPI0_SIN */

  PORTB->PCR[4]|=PORT_PCR_MUX(3); /* Port B16: MUX = ALT3, LPSPI0_SOUT */

  PORTB->PCR[5]|=PORT_PCR_MUX(4); /* Port B17: MUX = ALT3, LPSPI0_PCS3 */

 

}

 

 

 

int counter, accumulator = 0, limit_value = 1000000;

 

 

 

int main(void) {

    counter = 0;

    uint32_t counter = 0;

 

    WDOG_disable();

    SOSC_init_8MHz();        /* Initialize system oscillator for 8 MHz xtal */

    SPLL_init_160MHz();      /* Initialize SPLL to 160 MHz with 8 MHz SOSC */

    NormalRUNmode_80MHz();   /* Init clocks: 80 MHz sysclk & core, 40 MHz bus, 20 MHz flash */

    LPSPI0_init_master();    /* Initialize LPSPI 1 as master */

    PORT_init();             /* Configure ports */

 

    for(;;) {

       LPSPI0_16bits_read=0xA;

       LPSPI0_transmit_16bits(tx_16bits);       /* Transmit half word (16 bits) on LPSPI0 */

      //LPSPI0_16bits_read = LPSPI0_receive_16bits(); /* Receive half word on LPSPI0 */

       counter++;

     }

 

 

    for (;;) {

        counter++;

 

        if (counter >= limit_value) {

            __asm volatile ("svc 0");

            counter = 0;

        }

    }

    /* to avoid the warning message for GHS and IAR: statement is unreachable*/

    __NO_RETURN

    return 0;

}

 

__INTERRUPT_SVC void SVC_Handler() {

    accumulator += counter;

}

 

 

LPSPI.c

#include "S32K144.h" /* include peripheral declarations S32K144 */

#include "LPSPI.h"

void LPSPI0_init_master(void) {

  PCC->PCCn[PCC_LPSPI0_INDEX] = 0;          /* Disable clocks to modify PCS ( default) */

  PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */

  LPSPI0->CR    = 0x00000000;   /* Disable module for configuration */

  LPSPI0->IER   = 0x00000000;   /* Interrupts not used */

  LPSPI0->DER   = 0x00000000;   /* DMA not used */

  LPSPI0->CFGR0 = 0x00000000;   /* Defaults: */

                                /* RDM0=0: rec'd data to FIFO as normal */

                                /* CIRFIFO=0; Circular FIFO is disabled */

                                /* HRSEL, HRPOL, HREN=0: Host request disabled */

  LPSPI0->CFGR1 = 0x00000001;   /* Configurations: master mode*/

                                /* PCSCFG=0: PCS[3:2] are enabled */

                                /* OUTCFG=0: Output data retains last value when CS negated */

                                /* PINCFG=0: SIN is input, SOUT is output */

                                /* MATCFG=0: Match disabled */

                                /* PCSPOL=0: PCS is active low */

                                /* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */

                                /* AUTOPCS=0: does not apply for master mode */

                                /* SAMPLE=0: input data sampled on SCK edge */

                                /* MASTER=1: Master mode */

  LPSPI0->TCR   = 0x5000000F;   /* Transmit cmd: PCS3, 16bits, prescale func'l clk by 4. */

                                /* CPOL=0: SCK inactive state is low */

                                /* CPHA=1: Change data on SCK lead'g, capture on trail'g edge*/

                                /* PRESCALE=2: Functional clock divided by 2**2 = 4 */

                                /* PCS=3: Transfer using PCS3 */

                                /* LSBF=0: Data is transferred MSB first */

                                /* BYSW=0: Byte swap disabled */

                                /* CONT, CONTC=0: Continuous transfer disabled */

                                /* RXMSK=0: Normal transfer: rx data stored in rx FIFO */

                                /* TXMSK=0: Normal transfer: data loaded from tx FIFO */

                                /* WIDTH=0: Single bit transfer */

                                /* FRAMESZ=15: # bits in frame = 15+1=16 */

  LPSPI0->CCR   = 0x04090808;   /* Clk dividers based on prescaled func'l clk of 100 nsec */

                                /* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */

                                /* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */

                                /* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */

                                /* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */

  LPSPI0->FCR   = 0x00000003;   /* RXWATER=0: Rx flags set when Rx FIFO >0 */

                                /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */

  LPSPI0->CR    = 0x00000009;   /* Enable module for operation */

                                /* DBGEN=1: module enabled in debug mode */

                                /* DOZEN=0: module enabled in Doze mode */

                                /* RST=0: Master logic not reset */

                                /* MEN=1: Module is enabled */

}

void LPSPI0_transmit_16bits (uint16_t send) {

  while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);

                                   /* Wait for Tx FIFO available */

  LPSPI0->TDR = send;              /* Transmit data */

  LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */

}

uint16_t LPSPI0_receive_16bits (void) {

  uint16_t receive = 0;

  while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);

                                   /* Wait at least one RxFIFO entry */

  receive= LPSPI0->RDR;            /* Read received data */

  LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */

  return receive;                  /* Return received data */

}

 

0 Kudos
973 Views
chris21
Contributor II

The sbc supplies my uc with power.

0 Kudos
954 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@chris21

      There is another possible reason, try to read these two registers.
      You can test whether the CAN function is working normally, because the external CAN signal can wake up the SBC, and you can access all the registers through SPI when it wakes up. If CAN communication is normal, I think the probability of hardware problems is very small.

Senlent_0-1628589510078.png

 

0 Kudos
958 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@chris21

         I am not familiar with register configuration ( GHS). According to your description, you have successfully debugged the SPI module on the EVB, but failed on your own PCB. Can software problems be ruled out? Is it possible to use jumpers to connect the EVB to the UJA1167 on the PCB? In this way, the cause of the problem can be easily found out.

        I have used other models of SBC before and encountered problems caused by the power supply of the debugger. Try don't connect the debugger when testing, use an oscilloscope to check whether there is a waveform on the SCK pin when power is on。

       This is all the methods I can think of.

BR!

Jim.

0 Kudos
937 Views
chris21
Contributor II

It seems to work now.

I took all file and made up a new project with them

While making a diff and studiing the files for in project, I found out that eclipse was using files from my origan .zip file.

I used this .zip file at import. This behavoir is very strange behavoir for me.

This was coded in startup.d:

//<myname>/profdaten/<myname>/Eigene\ Dateien/SBC_1169.ZIP_expanded/SBC_1167/include/startup.h \
//<myname>/profdaten/<myname>/Eigene\ Dateien/SBC_1169.ZIP_expanded/SBC_1167/include/device_registers.h \

...and it should look like this

C:/..<myname>../workspaceS32DS.3.4/TESTING1/include/startup.h \
C:/..<mynamw>../workspaceS32DS.3.4/TESTING1/include/device_registers.h \

Nevermind. This fault costs me 2 days. If I would have a better understanding using eclipse, I

like eclipse a bit more. From my point of view a simple.bat file in combination with Notepad++, will do also.

 

0 Kudos