Promlem about FlexI2C on S32k118

[Xiao-xiao-pang]

hello，

• I hope someone can help me solve this problem

The chip I use is S32K118. In the process of sending data using flex2c, I found that SDA began to modify the data immediately after the SCL changed from high level to low level, but the data retention interval of standard I2C was not satisfied. Can you do this by configuring registers? The data modification time of the SDA pin occurs after the SCL clock has been low for a period of time。

Waveform collected by oscilloscope：

Desired waveform：

[Daniel-Aguirre]

Hi,

The measurement for t_HD;DAT must be made from the 0.3*Vdd on the SCL to the respective level threshold on the SDA side (either 0.3*Vdd or 0.7*Vdd, depending on what level is the bit that needs to be hold). This value should be between 0 and 3.45us for the first configuration and from 0 to 0.9us for the last one (at least on that specific table you are showing).

From the image you are sending, we cannot see this measurement being done. We are seeing the measurement from 0.7*Vdd on SCL to 0.7*Vdd on SCL (or the period of SCL). You may want to modify your measurement to be between 0.3*Vdd on SCL and the respective 0.3*Vdd or 0.7*Vdd on the SDA side. This should be inside the time it is specified by the I²C standard.

As to the register configuration, in Table 52-8 it is mentioned the timing parameters that can be modified in order to accomplish the I²C standard [Page 1643, S32K1xx Series Reference Manual, Rev. 13, 04/2020].

Please, let us know if this information was helpful or not.

[Xiao-xiao-pang]

hello，

   What I see in the Table 52-8 is the LPI2C configuration table, not flexI2C。

I drew an ugly expected shape, so I think I can draw it out

[Daniel-Aguirre]

Hi,

We do apologize for the confusion. Regarding FelxI²C, it is said the following:

"The I2C master data valid is delayed 2 cycles because the clock output is passed through a synchronizer before clocking the transmit/receive shifter (to guarantee some SDA hold time)" [Page 1782, S32K1xx Series Reference Manual, Rev. 13, 04/2020].

The hold time seems to be delayed 2 clock cycles of the FlexIO clock frequency. This seems to be an architecture dependent time, does not seem to be a register to modify this.

But again, we do see the data is being hold at least the minimum time (for the capture you sent). Could you take the same capture with more zoom on the zone of interest?

Please, let us know if this information helps you or not.

[Xiao-xiao-pang]

hello，

    Data hold time is almost zero.The sda shift output is triggered by time clock, when the scl is pulled down, the sda output is triggered.

[Daniel-Aguirre]

Hi,

The stated time is to be higher than 0. The following is said:

"Ensure SCL drops below 0.3VDD on falling edge before SDA crosses into the indeterminate range of 0.3 VDD to 0.7 VDD." [Page 44, UM10204 I2C-bus specification and user manual, Rev 7.0, 10/2021].

As you are saying, if it is almost 0 but still higher than 0, then it is inside the I²C standard.

Please, let us know if this information helps you or not.