When developing with S32K311, an external crystal oscillator of 16 MHz is selected. When configuring CANFD, the CAN clock source uses the AIPS_PLAT_CLK at 60 MHz. 80% sampling point is configured for the data field, and TDC is enabled. However, the actual measured sampling point in CANOE can only reach 72%.
This issue also occurs in tests on other models such as the S32K312 and S32K342.
The following is one of our configurations where we set the sampling points and test data. We configured the sampling point to be 76%, but the actual test result was 67%.
For CAN FD data phase the latest possible sample point must be set in CANoe. Then the VH6501 sends frames and lengthens the individual bits by one tick after each interval.
This seems to be a configuration issue with your VH6501. You can try modifying the parameters here to 70%, 76.667%, and 80% and then testing again.
We consulted several experienced engineers. They described that there are also problems with the small sampling point test in S32K1 and K3, and this problem may not be strongly related to the MCU.However, the test results vary when different testing instruments are used. When using CANoe for testing, the test results are all on the low side. They suggest that the sampling point configured for S32K3 can be appropriately increased under the actual test requirement of 80%. You can use any NXP demo to conduct a test, and this phenomenon should be reproducible.
This should still be a testing issue, not caused by the MCU.
However, I will spend some time doing some simple tests. I will probably use an oscilloscope to test directly, which should be the most accurate measurement method.
If you have more convincing results, please share them with us as well. We used some other instruments for testing, and the obtained sampling points are relatively close to what we expected in the settings. However, for customers, CANoe has a very high level of industry recognition.