PFLASH configuration not changing access to flash behaviour

[fgolubic]

On S32K344 enabling prefetch and buffering on flash controller does not produce any visible difference when reading from flash memory. As far as I understand Technical Reference manual for S32Kxx enabling Prefetch and Data Buffers should result in shorter reading time, overall, from flash memory after first read. 

However, that doesn't happen in my case - every read takes the same time regardless of Data Buffers or Prefetch being enabled or disabled.

My S32K344 also has disabled lockstep so we are using both Core1 and Core0.  So for both PCRF0 and PCRF1 registers PxDP, PxCP, PxDB and PxCB fields are enabled. Reading is done from task that is run on Core0.

Following Technical Reference Manual registers are set before starting second core and code execution is in system RAM.

Is there anything else or any additional feature that needs to be activated for PFLASH to work as suggested above?

Reading from flash was tried on a couple of memory locations inside flash with different data varying between 50 bytes and 900 bytes. 

Additionally, after inspecting memory location of PFCR registers in raw memory it seems that each core uses different endianness.

Core1 memory snapshot of PFCR0: 

Core0 memory snapshot of PFCR0:

It is the same for PFCR1. It looks like from the likes of Technical Reference that this cannot be changed. Also, registers on other memory locations do not have this issue.

Another question is whether this is something that could impact work of PFLASH or it has nothing to do with the issue at hand.

Thanks in advance.

[fgolubic]

I did activate P0 and P2. I also tried any combination of P0, P1 and P3 and I see no changes in timing when reading from flash repeatedly. Also tried only on one core running an application with P0 and I see no changes in timing when reading from flash repeatedly. 

My conclusion drawn from Reference Manual is that either something is not configured or every time I try to read flash it generates cache miss (although I am reading the same, unchanged data) and flash controller accesses flash memory directly.

As Technical Reference is not elaborate on how cache in flash controller is working, could you share some insight in it?

[davidtosenovjan]

Can you described method how you read PCFR0 registers? It does not make sense to read different value by each code, they surely do not use different endianness.

Second point is whether during these tests you have disabled data and instruction caches (otherwise it could be difficult to see differences between flash pre-fetching during such isolated tests).

[davidtosenovjan]

You need to configure different registers than you mentioned (P0 and P2). Otherwise I think there is nothing more to configure.