Ofloading periodic multiple channel ADC with PDB+DMA

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Ofloading periodic multiple channel ADC with PDB+DMA

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kef2
Senior Contributor IV

Hi

 

I want to perform periodic ADC reads on multiple channels. I’d like to collect several samples of the same channel prior to interrupting CPU, multiple channels simultaneously. PCB is done already; both ADC0 and ADC1 will sample about 5-6 channels. Please fix my thoughts or suggest better solution.

I place destination buffer at 2^DMA.TCD.DMOD aligned location. DMA.TCD.NBYTES is 4*8 (8 channels instead of 5-6 required, but major DMA loop aligns with DMOD) after N samples.

Since DMA.TCD.SLAST applies to major loop, I can’t use it the way I want. Using SLAST is fine for single sample (snapshot of) of multiple ADC channels and DMA interrupt after each sample. For interrupt after multiple samples, I need to use DMA source address modulo (SMOD) feature and use ADC registers starting from one, which is SMOD aligned. SMOD should be 5, 2^5=32 = 8 samples * sizeof(ADC register). Unfortunately ADC RA register is not 32 bytes aligned. Instead of using ADC result registers RA-RH (offsets 0x48..0x67), it seems I need to use RG-RN (offsets 0x60..0x7F).

Is above correct or am I’m complicating something? I managed to make PDB in BB+CONT mode triggering periodic ADC samples, but using DMA SLAST instead of SMOD, so interrupt after every sample. I hope PDB won’t show stop interrupt every Nth sample.

 

Edward

 

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

 you can try to enable Minor loop mapping and use minor loop offset for Source, see more in DMA chapter of the RM.

You can refer also here https://community.nxp.com/t5/S32K/trigger-one-time-DMA-after-5-ADC-channel-and-every-channel-get/m-p...

 

BR, Petr

 

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

 you can try to enable Minor loop mapping and use minor loop offset for Source, see more in DMA chapter of the RM.

You can refer also here https://community.nxp.com/t5/S32K/trigger-one-time-DMA-after-5-ADC-channel-and-every-channel-get/m-p...

 

BR, Petr

 

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kef2
Senior Contributor IV

Hi Petr,

Thanks. More DMA channels used, but much more flexible.

Edward

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kef2
Senior Contributor IV

I thought it will take me more time to change PDB settings for what I want. Yeah, seems working.

What I don't like is that back to back operation is applicable only to the same PDB channel. Would be nice to start from PDB0->CH[0].DLY[6] and continue with all PDB0->CH[1] pre-triggers. But indeed PDB0->CH[1].DLY[0] should be fine tuned for faster sample rate. And since RM tells that for better results ADC0 and ADC1 should be not calibrated simultaneously, I think these PDB delays should make be so ADC0 and ADC1 never convert simultaneously.

Edward

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