/******************************************************************************
*
* NXP(TM) and the NXP logo are trademarks of NXP.
* All other product or service names are the property of their respective owners.
* (C) Freescale Semiconductor, Inc. 2013-2016
* Copyright 2024 NXP
*
* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF NXP.
*
* Description: Configuration Header file
*
* Note: The implementation that was used is: AUTOSAR_S32K3xx
* System Generator for AUTOSAR OS/S32K3xx - Version: 4.7 Build 4.7.152
*
********************************************************************************/
#ifndef OSCFG_H
#define OSCFG_H
/* Applications */
#define OsApplication0 ((ApplicationType)OS_MKOBJID(OBJECT_APPLICATION, 0U)) /* Application ID */
/* Spinlock */
/* Application modes */
#define OsAppMode0 ((AppModeType)0U) /* AppMode ID */
/* Common stack */
#define OSTask10msSTKSIZE 1032U /* stack size of Task10ms */
#define OSTask10msSTKBOS OSRUNNABLESTKBEG /* Task10ms bos */
#define OSTask10msSTKTOS ((OSTask10msSTKBOS) + (OSTask10msSTKSIZE/4U)) /* Task10ms tos */
#define OSTask1sSTKSIZE 1032U /* stack size of Task1s */
#define OSTask1sSTKBOS OSTask10msSTKTOS /* Task1s bos */
#define OSTask1sSTKTOS ((OSTask1sSTKBOS) + (OSTask1sSTKSIZE/4U)) /* Task1s tos */
#define OSDSP2_SPI_TaskSTKSIZE 1032U /* stack size of DSP2_SPI_Task */
#define OSDSP2_SPI_TaskSTKBOS OSTask1sSTKTOS /* DSP2_SPI_Task bos */
#define OSDSP2_SPI_TaskSTKTOS ((OSDSP2_SPI_TaskSTKBOS) + (OSDSP2_SPI_TaskSTKSIZE/4U)) /* DSP2_SPI_Task tos */
#define OSDSP1_SPI_TaskSTKSIZE 1032U /* stack size of DSP1_SPI_Task */
#define OSDSP1_SPI_TaskSTKBOS OSDSP2_SPI_TaskSTKTOS /* DSP1_SPI_Task bos */
#define OSDSP1_SPI_TaskSTKTOS ((OSDSP1_SPI_TaskSTKBOS) + (OSDSP1_SPI_TaskSTKSIZE/4U)) /* DSP1_SPI_Task tos */
#define OSBIPC_NonBlk_Sync_TaskSTKSIZE 1032U /* stack size of BIPC_NonBlk_Sync_Task */
#define OSBIPC_NonBlk_Sync_TaskSTKBOS OSDSP1_SPI_TaskSTKTOS /* BIPC_NonBlk_Sync_Task bos */
#define OSBIPC_NonBlk_Sync_TaskSTKTOS ((OSBIPC_NonBlk_Sync_TaskSTKBOS) + (OSBIPC_NonBlk_Sync_TaskSTKSIZE/4U)) /* BIPC_NonBlk_Sync_Task tos */
#define OSDspPlatCom_ResponseTaskSTKSIZE 1032U /* stack size of DspPlatCom_ResponseTask */
#define OSDspPlatCom_ResponseTaskSTKBOS OSBIPC_NonBlk_Sync_TaskSTKTOS /* DspPlatCom_ResponseTask bos */
#define OSDspPlatCom_ResponseTaskSTKTOS ((OSDspPlatCom_ResponseTaskSTKBOS) + (OSDspPlatCom_ResponseTaskSTKSIZE/4U)) /* DspPlatCom_ResponseTask tos */
#define OSTalariaResponse_TaskSTKSIZE 1032U /* stack size of TalariaResponse_Task */
#define OSTalariaResponse_TaskSTKBOS OSDspPlatCom_ResponseTaskSTKTOS /* TalariaResponse_Task bos */
#define OSTalariaResponse_TaskSTKTOS ((OSTalariaResponse_TaskSTKBOS) + (OSTalariaResponse_TaskSTKSIZE/4U)) /* TalariaResponse_Task tos */
#define OSRMDLControl_TaskSTKSIZE 1032U /* stack size of RMDLControl_Task */
#define OSRMDLControl_TaskSTKBOS OSTalariaResponse_TaskSTKTOS /* RMDLControl_Task bos */
#define OSRMDLControl_TaskSTKTOS ((OSRMDLControl_TaskSTKBOS) + (OSRMDLControl_TaskSTKSIZE/4U)) /* RMDLControl_Task tos */
#define OSNVRAM_TaskSTKSIZE 1032U /* stack size of NVRAM_Task */
#define OSNVRAM_TaskSTKBOS OSRMDLControl_TaskSTKTOS /* NVRAM_Task bos */
#define OSNVRAM_TaskSTKTOS ((OSNVRAM_TaskSTKBOS) + (OSNVRAM_TaskSTKSIZE/4U)) /* NVRAM_Task tos */
/* Task definitions */
#define Task1ms ((TaskType)OS_MKOBJID(OBJECT_TASK, 0U)) /* Task ID */
extern void FuncTask1ms(void); /* Task entry point */
#define Task10ms ((TaskType)OS_MKOBJID(OBJECT_TASK, 1U)) /* Task ID */
extern void FuncTask10ms(void); /* Task entry point */
#define Task100ms ((TaskType)OS_MKOBJID(OBJECT_TASK, 2U)) /* Task ID */
extern void FuncTask100ms(void); /* Task entry point */
#define Task1s ((TaskType)OS_MKOBJID(OBJECT_TASK, 3U)) /* Task ID */
extern void FuncTask1s(void); /* Task entry point */
#define DSP2_SPI_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 4U)) /* Task ID */
extern void FuncDSP2_SPI_Task(void); /* Task entry point */
#define DSP1_SPI_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 5U)) /* Task ID */
extern void FuncDSP1_SPI_Task(void); /* Task entry point */
#define BIPC_NonBlk_Sync_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 6U)) /* Task ID */
extern void FuncBIPC_NonBlk_Sync_Task(void); /* Task entry point */
#define DspPlatCom_ResponseTask ((TaskType)OS_MKOBJID(OBJECT_TASK, 7U)) /* Task ID */
extern void FuncDspPlatCom_ResponseTask(void); /* Task entry point */
#define TalariaResponse_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 8U)) /* Task ID */
extern void FuncTalariaResponse_Task(void); /* Task entry point */
#define RMDLControl_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 9U)) /* Task ID */
extern void FuncRMDLControl_Task(void); /* Task entry point */
#define NVRAM_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 10U)) /* Task ID */
extern void FuncNVRAM_Task(void); /* Task entry point */
#define InitTask ((TaskType)OS_MKOBJID(OBJECT_TASK, 11U)) /* Task ID */
extern void FuncInitTask(void); /* Task entry point */
/* ISR functions */
#define OS_isr_SIUL2_EXT_IRQ_0_7_ISR SIUL2_EXT_IRQ_0_7_ISR
/* ISRs definition */
#define OSISREMIOS1_4_IRQ() OSISR2DISP(EMIOS1_4_IRQ) /* IrqChannel is EXTERNAL */
extern void OS_isr_EMIOS1_4_IRQ(void); /* irq: EMIOS1_4_IRQ; channel: EXTERNAL; category: 2 */
#define EMIOS1_4_IRQLEVEL 4U /* interrupt level of EMIOS1_4_IRQ */
#define EMIOS1_4_IRQPRIORITY 4U /* priority of EMIOS1_4_IRQ */
#define OSISRLPI2C0_Master_Slave_IRQHandler() OSISR2DISP(LPI2C0_Master_Slave_IRQHandler) /* IrqChannel is EXTERNAL */
extern void OS_isr_LPI2C0_Master_Slave_IRQHandler(void); /* irq: LPI2C0_Master_Slave_IRQHandler; channel: EXTERNAL; category: 2 */
#define LPI2C0_Master_Slave_IRQHandlerLEVEL 5U /* interrupt level of LPI2C0_Master_Slave_IRQHandler */
#define LPI2C0_Master_Slave_IRQHandlerPRIORITY 5U /* priority of LPI2C0_Master_Slave_IRQHandler */
#define OSISRLPI2C1_Master_Slave_IRQHandler() OSISR2DISP(LPI2C1_Master_Slave_IRQHandler) /* IrqChannel is EXTERNAL */
extern void OS_isr_LPI2C1_Master_Slave_IRQHandler(void); /* irq: LPI2C1_Master_Slave_IRQHandler; channel: EXTERNAL; category: 2 */
#define LPI2C1_Master_Slave_IRQHandlerLEVEL 5U /* interrupt level of LPI2C1_Master_Slave_IRQHandler */
#define LPI2C1_Master_Slave_IRQHandlerPRIORITY 5U /* priority of LPI2C1_Master_Slave_IRQHandler */
#define OSISRLpspi_Ip_LPSPI_5_IRQHandler() OSISR2DISP(Lpspi_Ip_LPSPI_5_IRQHandler) /* IrqChannel is EXTERNAL */
extern void OS_isr_Lpspi_Ip_LPSPI_5_IRQHandler(void); /* irq: Lpspi_Ip_LPSPI_5_IRQHandler; channel: EXTERNAL; category: 2 */
#define Lpspi_Ip_LPSPI_5_IRQHandlerLEVEL 5U /* interrupt level of Lpspi_Ip_LPSPI_5_IRQHandler */
#define Lpspi_Ip_LPSPI_5_IRQHandlerPRIORITY 5U /* priority of Lpspi_Ip_LPSPI_5_IRQHandler */
#define OSISRMCL_FLEXIO_ISR() OSISR2DISP(MCL_FLEXIO_ISR) /* IrqChannel is EXTERNAL */
extern void OS_isr_MCL_FLEXIO_ISR(void); /* irq: MCL_FLEXIO_ISR; channel: EXTERNAL; category: 2 */
#define MCL_FLEXIO_ISRLEVEL 5U /* interrupt level of MCL_FLEXIO_ISR */
#define MCL_FLEXIO_ISRPRIORITY 5U /* priority of MCL_FLEXIO_ISR */
#define OSISRPIT_0_ISR() OSISR2DISP(PIT_0_ISR) /* IrqChannel is EXTERNAL */
extern void OS_isr_PIT_0_ISR(void); /* irq: PIT_0_ISR; channel: EXTERNAL; category: 2 */
#define PIT_0_ISRLEVEL 2U /* interrupt level of PIT_0_ISR */
#define PIT_0_ISRPRIORITY 2U /* priority of PIT_0_ISR */
#define OSISRPIT_1_ISR() OSISR2DISP(PIT_1_ISR) /* IrqChannel is EXTERNAL */
extern void OS_isr_PIT_1_ISR(void); /* irq: PIT_1_ISR; channel: EXTERNAL; category: 2 */
#define PIT_1_ISRLEVEL 3U /* interrupt level of PIT_1_ISR */
#define PIT_1_ISRPRIORITY 3U /* priority of PIT_1_ISR */
#define OSISRSIUL2_EXT_IRQ_0_7_ISR() OSISR2DISP(SIUL2_EXT_IRQ_0_7_ISR) /* IrqChannel is EXTERNAL */
extern void OS_isr_SIUL2_EXT_IRQ_0_7_ISR(void); /* irq: SIUL2_EXT_IRQ_0_7_ISR; channel: EXTERNAL; category: 2 */
#define SIUL2_EXT_IRQ_0_7_ISRLEVEL 5U /* interrupt level of SIUL2_EXT_IRQ_0_7_ISR */
#define SIUL2_EXT_IRQ_0_7_ISRPRIORITY 5U /* priority of SIUL2_EXT_IRQ_0_7_ISR */
#define OSISRSIUL2_EXT_IRQ_16_23_ISR() OSISR2DISP(SIUL2_EXT_IRQ_16_23_ISR) /* IrqChannel is EXTERNAL */
extern void OS_isr_SIUL2_EXT_IRQ_16_23_ISR(void); /* irq: SIUL2_EXT_IRQ_16_23_ISR; channel: EXTERNAL; category: 2 */
#define SIUL2_EXT_IRQ_16_23_ISRLEVEL 5U /* interrupt level of SIUL2_EXT_IRQ_16_23_ISR */
#define SIUL2_EXT_IRQ_16_23_ISRPRIORITY 5U /* priority of SIUL2_EXT_IRQ_16_23_ISR */
#define OSISRSTM_0_ISR() OSISR2DISP(STM_0_ISR) /* IrqChannel is EXTERNAL */
extern void OS_isr_STM_0_ISR(void); /* irq: STM_0_ISR; channel: EXTERNAL; category: 2 */
#define STM_0_ISRLEVEL 1U /* interrupt level of STM_0_ISR */
#define STM_0_ISRPRIORITY 1U /* priority of STM_0_ISR */
#define EMIOS1_4_IRQ ((ISRType)OS_MKOBJID(OBJECT_ISR, 0U)) /* ISR ID */
#define LPI2C0_Master_Slave_IRQHandler ((ISRType)OS_MKOBJID(OBJECT_ISR, 1U)) /* ISR ID */
#define LPI2C1_Master_Slave_IRQHandler ((ISRType)OS_MKOBJID(OBJECT_ISR, 2U)) /* ISR ID */
#define Lpspi_Ip_LPSPI_5_IRQHandler ((ISRType)OS_MKOBJID(OBJECT_ISR, 3U)) /* ISR ID */
#define MCL_FLEXIO_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 4U)) /* ISR ID */
#define PIT_0_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 5U)) /* ISR ID */
#define PIT_1_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 6U)) /* ISR ID */
#define SIUL2_EXT_IRQ_0_7_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 7U)) /* ISR ID */
#define SIUL2_EXT_IRQ_16_23_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 8U)) /* ISR ID */
#define STM_0_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 9U)) /* ISR ID */
/* ISR1 id */
/* Resources definitions */
#define A2B_I2C_RESOURCE ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 0U)) /* Resource ID */
#define BIPC_Alarm_Resource ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 1U)) /* Resource ID */
#define BIPC_Non_Blk_Mutex ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 2U)) /* Resource ID */
#define MCAPI_Event_Handler ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 3U)) /* Resource ID */
#define NVRAM_RequestList ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 4U)) /* Resource ID */
#define NVRAM_RequestQueue ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 5U)) /* Resource ID */
#define OsResource_FG1 ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 6U)) /* Resource ID */
#define RES_SCHEDULER ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 7U)) /* Resource ID */
/* Events definition */
#define DSP_SPI_Rx_Ready ((EventMaskType)4U) /* Event mask */
#define DSP_SPI_Tx_Ready ((EventMaskType)2U) /* Event mask */
#define DSP_SPI_Wait_Complete ((EventMaskType)64U) /* Event mask */
#define MCAPI_NONBLK_EVENT ((EventMaskType)256U) /* Event mask */
#define MCAPI_TIMEOUT_EVENT ((EventMaskType)512U) /* Event mask */
#define MCAPI_Timeout_Task_Event ((EventMaskType)65536U) /* Event mask */
#define MCAPI_WAKEUP_EVENT ((EventMaskType)8U) /* Event mask */
#define NVRAM_Event ((EventMaskType)32U) /* Event mask */
#define NVRAM_Queue_Event ((EventMaskType)131072U) /* Event mask */
#define RMDLControl_Event ((EventMaskType)2048U) /* Event mask */
/* Alarms identification */
#define DSP1_SPI_Wait_Alarm ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 0U)) /* Alarm ID */
#define MCAPI_NonBlk_Sync_Alarm ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 1U)) /* Alarm ID */
#define NVRAM_TimeoutAlarm ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 2U)) /* Alarm ID */
#define NVRAM_TimeoutQueueAlarm ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 3U)) /* Alarm ID */
#define OsAlarm_1ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 4U)) /* Alarm ID */
#define OsAlarm_ASW_100ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 5U)) /* Alarm ID */
#define OsAlarm_ASW_10ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 6U)) /* Alarm ID */
#define OsAlarm_BSW_100ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 7U)) /* Alarm ID */
#define OsAlarm_BSW_10ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 8U)) /* Alarm ID */
/* Counters identification */
#define OsCounter_0 ((CounterType)OS_MKOBJID(OBJECT_COUNTER, 0U)) /* Counter ID */
#define OSMINCYCLE_OsCounter_0 ((TickType)0x1U) /* OsCounter_0 */
#define OSMAXALLOWEDVALUE_OsCounter_0 ((TickType)0xffffffffU) /* OsCounter_0 */
#define OSTICKSPERBASE_OsCounter_0 1UL /* OsCounter_0 */
#define OS_TICKS2NS_OsCounter_0(ticks) (PhysicalTimeType)((ticks)*10000U) /* */
#define OS_TICKS2US_OsCounter_0(ticks) (PhysicalTimeType)(((OSQWORD)(ticks))*10000ULL/1000UL) /* */
#define OS_TICKS2MS_OsCounter_0(ticks) (PhysicalTimeType)(((OSQWORD)(ticks))*10000ULL/1000000UL) /* */
#define OS_TICKS2SEC_OsCounter_0(ticks) (PhysicalTimeType)(((OSQWORD)(ticks))*10000ULL/1000000000UL) /* */
#define OSMINCYCLE ((TickType)0x1U) /* SysTimer */
#define OSMAXALLOWEDVALUE ((TickType)0xffffffffU) /* SysTimer */
#define OSTICKSPERBASE 1UL /* SysTimer */
#define OSTICKDURATION 10000UL /* SysTimer */
/* Messages identification */
/* Flags identification */
/* Message callback prototypes */
/* scheduletable */
#define APP_STOP_SEC_CODE
#include "Os_memmap.h"
#define OS_START_SEC_CONST_UNSPECIFIED
#define OS_STOP_SEC_CONST_UNSPECIFIED
#endif /* OSCFG_H */