MPU organization reference design s32k324

[michelet1]

hello,

i was studying code for the following reference design: https://www.nxp.com/design/design-center/development-boards-and-designs/automotive-development-platf...

I was focusing on the mechanism of using the MPU in this example but 3 doubts emerged:

1)the definitive addresses in the MPU in core0 are the same as those defined in core1, is this procedure correct? shouldn't each core define addresses for its own memory area in the MPU?

2)shouldn't the addresses defined in the MPU be tied to specific areas of the linker script?

3)in the MPU Config:  RegionConfig_5(start from 0x20400000 to 0x2042FFFF) is partially overlapping with RegionConfig_10(start from 0x20424000 to 0x20427FFF).  

Why are two overlapping areas managed within the MPU? are there specific reasons to implement a mechanism of this kind?

Any help of info on this would be welcome. thanks for collaboration 

[jianqiuhu]

Hello,

In the reference SW, only the RegionConfig_10(start from 0x20424000 to 0x20427FFF) of the 

MPU_M7_ModuleConfig_0 structure is used. So no conflict there.

You can find the comments in the source file.

[michelet1]

hi @jianqiuhu ,

thanks for the informations.

i still have some doubts about your reply:

1)both core recall region10( Mpu_M7_Ip_SetRegionConfig(14, &Mpu_M7_Config.pRegionConfigArr[10])  ) in their main. Wasn't it enough for only one core(for example core0) to invoke this initialization? why in this case is it necessary for both cores to manage the initialization of the MPU Region 10?

2)What is the point of having managed a configuration table with 11 MPU memory areas(MPU_M7_Config) when only area 10 is initialized and therefore used in the main?From the code it is also not clear why area 10 is initialized, what is the reason for specifically protecting the memory addresses linked to this area?

Thanks again for your precious help and collaboration 

[jianqiuhu]

Hi,

Regarding the MPU, each core has it's own MPU to configure the memory properties. So both core0 and core1 should call the MPU API to configure the sharable memory, described in the Mpu_M7_Config.pRegionConfigArr[10], for dual-core communication IPCF.

The region number here is 14 is because region0~region13 have been configured at the silicon startup stage, you can find in the system.c

The reason that we just use the region10 but with a 11 size configuration table is  when you adding the MPU module to the project, some default configurations will be added automatically, but we do not use them. We just added the region10 behind the default configurations for more comprehensive.

[michelet1]

Hello,

thanks for your help.

His answer was clear except for the last point:

"The reason that we just use the region10 but with a 11 size configuration table is  when you adding the MPU module to the project, some default configurations will be added automatically, but we do not use them. We just added the region10 behind the default configurations for more comprehensive."

I didn't understand how these default configurations are added automatically. I tried to delete IPV_Mpu_M7_Ip block under the configuration tool and then create it again but it didn't add any default blocks.(I've also attached an image).

thanks again for your precious help and collaboration

[michelet1]

hello @jianqiuhu ,

his last answer was quite clear to me. if you could also clarify the last point which wasn't very clear to me i would  be very grateful.

thanks again for your precious help and availability

best regards