Hi
I support S32K but not familiar with FS26, so if it is a problem on FS26 side, I may ask my colleagues to help.
Please check whether the voltage of FS26_VLDO1, FS26_VLDO2, FS26_VCORE, and FS26_VREF is correct. If not, you need to burning OTP configuration: FS26xx OTP Instruction
Because your blank S32K322 does not have a program to feed the FS26 watchdog via SPI, it is recommended to first put the FS26 into debug mode to disable the watchdog.
Table 259. Electrical characteristics of FS26 DataSheet mentions that the VDBG voltage should be between 2.5-6v to allow FS26 to enter debug mode.
Please pay attention to modify the values of R119 and R114.
Please use an oscilloscope to measure the RESET_b pin waveform, which will help analyze whether the reset signal is caused by FS26 or S32K3.
You don't need to add L21 and L22. Please refer to 2.1.2.10 Bulk/Bypass and decoupling capacitors scheme for the S32K344 /42 /24 /22 /14 – 172HDQFP of S32K3xx - Hardware Design Guidelines -- Rev_E2.pdf.
There are some external pull-up resistors connected to the external power source(VCC_3V3 and FS26_VLDO1).
Note the chapter 12 Injection current of S32K3xx - Hardware Design Guidelines -- Rev_E2.pdf:
When the MCU is in an unpowered state, current injected through the chip pins may bias internal chip structures (for example, ESD diodes) and incorrectly power up these internal structures through inadvertent paths. The presence of such residual voltage may influence different chip-internal blocks in an unpredictable manner and may ultimately result in unpredictable chip behavior (for example, POR flag not set). Once in the illegal state, powering up the chip further and then applying reset will clear the illegal state. Injection current specified for the chip under the aspect of absolute maximum ratings represent the capability of the internal circuitry to withstand such condition without causing physical damage.
Best Regards,
Robin
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