LPSPI FRAMESZ and Receive Data Register

[vusal]

Hello,

I'm interfacing S32K3xx with an external flash memory. This chip requires different size command and data combinations. For example, to read the status register one needs to send 1 byte command and wait for 1 byte of data to appear on the MISO line. Frame size can range from 8 bits to several bytes. Is there a way to interface this chip without needing changing FRAMESZ each time?

In the above example, I couldn't just send 1 byte of command. I had to send an extra dummy byte to allow for the memory chip to respond. So, my frame size had to be 16 bits long. I have other use cases where I am sending 1 byte of command + 3 bytes of address + 10 bytes of data (just an example). It seem like each time my data changes I have to modify the FRAMESZ.

Another question: It seem like to get correct data in the SPI data register I have to read that register each time I send out a frame. Is this how the SPI set up?

LPSPI1_transmit_16bits(tx_16bits); /* Transmit half word (16 bits) on LPSPI1 */
LPSPI1_16bits_read = LPSPI1_receive_16bits(); /* Receive half word on LSPI1 */

Thank you very much for your help!

Vusal

[danielmartynek · Accepted solution]

Hello Vusal,

I understand you need to keep CS asserted throughout the whole 14-byte transfer (using the example, 1 byte of command + 3 bytes of address + 10 bytes of data).

For that, the LPSPI Continous mode can be used (TCR[CONT = 1]).

FRAMESZ can be set to 8bit frames.

The LPSPI will keep CS asserted until a new command with TCR[CONT = 0].

RTD LPSPI_IP driver

Call the function below with Length = 14.

Regards,

Daniel

[vusal]

Hi Daniel,

Thank you for your message. This fixed the issue.

One more quick question: It seem like to get correct data in the SPI data register I have to read that register each time I send out a frame. Is this how the SPI set up?

LPSPI1_transmit_16bits(tx_16bits); /* Transmit half word (16 bits) on LPSPI1 */
LPSPI1_16bits_read = LPSPI1_receive_16bits(); /* Receive half word on LSPI1 */


Thank you!

Best,
Vusal

[danielmartynek]

There is 4x32b RX FIFO disabled by default.

BR, Daniel

[vusal]

Thank you!