LPO Clock out of range

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LPO Clock out of range

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jingfang
Contributor IV

I test LPO Clock out of range, is there anything I can try?

I test five:

fail :109.9/111.9/112.4/110.9

pass:113.9

捕获.JPG

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jingfang
Contributor IV

We confirm that the 2 boards default to 0x19 & 0x1D, period of LPO clock is OK.

Does it mean that the value will be dynamically adjusted at the NXP factory? Does typ 128 written in the S32K-RM refer to the adjusted value instead of 0x00?Can you add this note to the S32K-RM? During initialization, the demo code changes this value,so we found the problem of clock out of range. Now we don't initialize,we just call PMC_SetLpoMode(PMC,TRUE);Is this modifcication OK? Or any other suggestions?

SDK_S32KXX_RTM_4.0.0;Version:component SDK_S32K14x_09

pic(28).jpgpic(30).jpgpic(32).jpg捕获1.JPG

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VaneB
NXP TechSupport
NXP TechSupport

Thanks for the feedback, I'll forward the information to the corresponding team in order to get it fixed.

Sorry for the inconvenience

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3,568 Views
jingfang
Contributor IV

Thank you very much. If there is any update, please inform me if it is convenient.

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3,589 Views
VaneB
NXP TechSupport
NXP TechSupport

The LPO is trimmed to a frequency close to 128kHz in the production, and LPOTRIM is loaded during the reset from the flash.

Regarding the problem with the demo code, I suggest you to update the SDK version to S32K1xx RTM 4.0.3. This software contains new features and also fixes issues with previous SDKs.
Please try using this new SDK and let me know if this makes any changes to the functionality of the project.

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3,581 Views
jingfang
Contributor IV

My customer has test 4.0.3,the problem still exists.

Spec show 0 = typ 128k,but it's actually adjusted to 128k,could you add a remark here?

捕获.JPG@VaneB 

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3,647 Views
VaneB
NXP TechSupport
NXP TechSupport

Hi @jingfang 

The working frequency of the LPO is tested at MCU level, so the frequency at which we guarantee its work is the one mentioned in the DS.

 

B.R.

VaneB

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3,643 Views
jingfang
Contributor IV

Are you meaning that the peripheral circuit could be biased?Which side in particular?

Custom change LPOTRIM ,-1 can be in range,the specific data are as follows:

NumberLPOTRIMMeasured DataDifference Data
A201190
-1122.33.3
A30109.60
-1114.34.7

 

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3,629 Views
jingfang
Contributor IV

Thanks a lot~

Q1: I mean that whether measured data is affected by the peripheral loop?

      因为你说,测试是由单MCU测试的,所以我想问:LPO的频率是否受外围回路影响?

Q2: If it's affected by the peripheral loop, I can check where?

       如果受外围回路影响,是哪些因素,我想请客人试试看,是不是那边导致?

Q3:I use 2 board,when LPOTRIM[4:0]  = 00000,LPO clock <113kHz,when LPOTRIM[4:0]  = 11111,LPO clock in spec,I want to make it clear that the default values are recommended.

我拿了2块板子测试LPO Clock,发现值<113kHz,我想看看是不是LPOTRIM设定导致,所以更改了一下值,发现LPOTRIM设定就是默认值。 企业微信截图_16657275448611.png

Q4:Yes,I use custom board.

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VaneB
NXP TechSupport
NXP TechSupport

The LPO frequency depends on process variations, and there are huge differences part-to-part. That is why the default value of LPOTRIM is not 0b00000, this is loaded during the reset from the flash.

You can read the register on you board, overwrite it, use CLKOUT to output LPO.

One LPOTRIM step is ~3kHz difference.

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VaneB
NXP TechSupport
NXP TechSupport

In order offer you a better help, could you help me clarify certain aspects of these questions
Q1: What do you mean "be biased"?
Q2: What do you mean "side"?
Q3: Could you explain the attached table?
Q4: Are you using a custom board?

Thank for your help

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