LPI2C related doubts

[vignesh3]

See LpI2C has only one transmit data register MDER.

Then how we can use the FIFO "LPI2C_Set_MasterTxFIFOWatermark" ?

can you give me some idea bout LpI2C fifo?

[vignesh3]

Hi @PetrS ,

can you tell me about the watermark is it like fifo threshold or what?

These fifo locations are not memory mapped right? so we can not directly access the fifo.

Can I use 2 fifo for RX and 2 for TX? 

If I can, how I need to configure the watermark for these requirement?

[PetrS · Accepted solution]

Hi,

yes, it is like fifo threshold, to determine when fifo flag is set.
Fifo is not memory mapped.
There is just 1 TX and 1 RX fifo.

BR, Petr

[PetrS]

Hi,

the LPI2C has 4 deep TX/RX FIFO. A MTDR register is used to write CMD+DATA or DATA into TXFIFO.
You should write MTDR when MSR(TDF) is set indicating whether transmit data is requested. This flag is set when the number of words in the transmit FIFO is equal or less than MFCR[TXWATER]. TXWATER is usually set to 3.

BR, Petr