Inconsistency in CAN receive interrupt

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Inconsistency in CAN receive interrupt

939 Views
cellprop
Contributor I

we are using 3.3V can transreciver with S32k144 as other end of CAN is connected to 3.3V can node.The project required to send CAN command to get some data from other node. The issue we are facing with s32k144 after sending multiple timed the can command the receive can interrupt is triggred
the distance between can node is 4m with baud rate of 250kbps.

The flexcan is configured to work in mailbox mode. following is the settings we have done.

Can you pls provide are we missing something as receive interrupt is not triggering properly

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

could you please describe the behavior in more detail? You wrote "the receive can interrupt is triggred" then "receive interrupt is not triggering properly". So what do you expect and what do you see?

For the code snippet; is the FLEXCAN_DRV_Init called after RX MB init, callback install etc? Hope not.
Global mask register is cleared, so you should receive all ext ID messages into prepared MB.

BR, Petr

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914 Views
cellprop
Contributor I

receive interrupt is not triggering properly" means that when s32k transmit a CAN command to a CAN node it responds back after multiple transmit from s32k.for e.g if i send a can command 16 times it responds back once.

I also debug the CAN node to find verify that it is receiving properly and the CAN node is working fine

 

For the code snippet; is the FLEXCAN_DRV_Init called after RX MB init, callback install etc?  its is only called once for initialization

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

unfortunately I did not get the point still.
You have 2 nodes, S32K144 and other CAN node. You wrote you see some receive interrupt issue on S32K node.
S32K node is sending CAN command, but this must be send multiple times in order to CAN node respond to it finally. So where is receive issue on S32K node?
Do you see any errors detected on S32K (see ESR1/ECR registers) to indicate lets say CAN bit timing inconsistency?

BR, Petr

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